[PATCH v2] riscv: smp: Align secondary_start_sbi to 4 bytes

[Vivian Wang]

On 4/15/26 20:37, Chen Pei wrote:

[...]

>>> In summary, it is more reasonable to make secondary_start_sbi
>>> satisfy 4-byte alignment.
>> Thus, it is unnecessary.
>>
>> If this fixes a bug where an interrupt can trap into the wrong stvec for
>> you, then your firmware is broken.
> This isn't about fixing a bug (as mentioned earlier, it's highly unlikely
> to happen),

It is *impossible* given correct HW and FW, but okay...

> but rather the STVEC check mechanism added to QEMU discovered
> this issue. Regarding the problem itself, I would appreciate any clarification
> or modifications from OpenSBI, but currently this modification is the simplest
> and most feasible.

The stvec CSR is WARL. If the "STVEC check mechanism" is complaining
about usage of CSRs as specified, then the check is a false positive and
is not something fixable.

Vivian "dramforever" Wang