[PATCH v2 2/2] iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits

[Tian, Kevin]

> From: fangyu.yu at linux.alibaba.com <fangyu.yu at linux.alibaba.com>
> Sent: Tuesday, April 14, 2026 7:02 PM
> 
> From: Fangyu Yu <fangyu.yu at linux.alibaba.com>
> 
> When the RISC-V IOMMU page table format support Svpbmt, PBMT provides
> a way to tag mappings with page-based memory types. Encode memory type
> via PBMT in RISC-V IOMMU PTEs:
> 
>   - IOMMU_MMIO   -> PBMT=IO
>   - !IOMMU_MMIO && !IOMMU_CACHE -> PBMT=NC
>   - otherwise    -> PBMT=Normal (PBMT=0)
> 
> Only touch PBMT when PT_FEAT_RISCV_SVPBMT is advertised.
> 
> Signed-off-by: Fangyu Yu <fangyu.yu at linux.alibaba.com>
> Reviewed-by: Jason Gunthorpe <jgg at nvidia.com>
> Reviewed-by: Anup Patel <anup at brainfault.org>
> Reviewed-by: Guo Ren <guoren at kernel.org>
> Reviewed-by: Nutty Liu <nutty.liu at hotmail.com>

Reviewed-by: Kevin Tian <kevin.tian at intel.com>