[PATCH v2] riscv: smp: Align secondary_start_sbi to 4 bytes

[Michael Ellerman]

On 13/4/2026 23:20, cp0613 at linux.alibaba.com wrote:
> From: Chen Pei <cp0613 at linux.alibaba.com>
> 
> During SMP boot, the secondary_start_sbi address is passed to the
> slave core via sbi_hsm_hart_start. In OpenSBI, this address is
> written to STVEC in sbi_hart_switch_mode.

...

> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index 9c99c5ad6fe8..9f33be6260e1 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -127,6 +127,7 @@ relocate_enable_mmu:
>   #endif /* CONFIG_MMU */
>   #ifdef CONFIG_SMP
>   	.global secondary_start_sbi
> +	.align 2
>   secondary_start_sbi:
>   	/* Mask all interrupts */
>   	csrw CSR_IE, zero


Minor nit, but IMHO .balign is preferable in new code. It always byte 
aligns, whereas .align has different meanings across architectures, and 
on some arches (including riscv) requires the reader to do the math to 
convert to a byte alignment.

These days there's also the SYM_CODE_START etc. macros defined via 
linkage.h, which use __ALIGN from arch/riscv/include/asm/linkage.h, 
which is already .balign 4.

cheers