[PATCH v1 02/13] dt-bindings: clock: Add system-0 domain PLL clock

[Changhuang Liang]

Hi, Krzysztof

> On 07/04/2026 08:56, Changhuang Liang wrote:
> > Hi, Krzysztof
> >
> > Thanks for the review.
> >
> >> On Thu, Apr 02, 2026 at 10:49:34PM -0700, Changhuang Liang wrote:
> >>> Add system-0 domain PLL clock for StarFive JHB100 SoC.
> >>>
> >>> Signed-off-by: Changhuang Liang <changhuang.liang at starfivetech.com>
> >>> ---
> >>>  .../bindings/clock/starfive,jhb100-pll.yaml   | 44
> +++++++++++++++++++
> >>>  .../dt-bindings/clock/starfive,jhb100-crg.h   |  6 +++
> >>
> >> You did not test your code. Apply patch #1 and test it. Do you see
> >> build-level errors?
> >
> > I'm very sorry about this. I will reorganize my patch to avoid the related
> errors.
> >
> 
> Anyway this one should be folded into the parent. You have one generic,
> system-wide clock as input, so as well this can be the resource of the parent.
> And no address spaces.
> 
> Other examples have one-register address spaces, so these are not really
> separate devices.

Just to confirm with you again.

The current version of dts is as follows:
			sys0_syscon: syscon at 13010000 {
				compatible = "starfive,jhb100-sys0-syscon", "syscon",
					     "simple-mfd";
				reg = <0x0 0x13010000 0x0 0x2000>;
				#address-cells = <2>;
				#size-cells = <2>;
				ranges = <0x0 0x0 0x0 0x13010000 0x0 0x2000>;

				sys0pll: clock-controller {
					compatible = "starfive,jhb100-sys0-pll";
					clocks = <&osc>;
					#clock-cells = <1>;
				};

				chipid at 38 {
					compatible = "starfive,jhb100-socinfo";
					reg = <0x0 0x38 0x0 0x4>;
				};
			};

In the next version, it will be changed to this, correct?

			sys0_syscon: syscon at 13010000 {
				compatible = "starfive,jhb100-sys0-syscon", "syscon";
				reg = <0x0 0x13010000 0x0 0x2000>;
				clocks = <&osc>;
				#clock-cells = <1>;
			};

Best Regards,
Changhuang