[PATCH v1 01/13] dt-bindings: soc: starfive: Add StarFive JHB100 syscon modules

[Krzysztof Kozlowski]

On 07/04/2026 09:34, Changhuang Liang wrote:
> Hi, Krzysztof
> 
> Thanks for the review.
> 
>> On Thu, Apr 02, 2026 at 10:49:33PM -0700, Changhuang Liang wrote:
>>> Add documentation to describe StarFive JHB100 SoC System Controller
>>> Registers.
>>>
>>> Signed-off-by: Changhuang Liang <changhuang.liang at starfivetech.com>
>>> ---
>>>  .../soc/starfive/starfive,jhb100-syscon.yaml  | 140
>> ++++++++++++++++++
>>>  MAINTAINERS                                   |   5 +
>>>  2 files changed, 145 insertions(+)
>>>  create mode 100644
>>> Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.
>>> yaml
>>>
>>> diff --git
>>> a/Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-sysco
>>> n.yaml
>>> b/Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-sysco
>>> n.yaml
>>> new file mode 100644
>>> index 000000000000..c0e1f6f68fa2
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-s
>>> +++ yscon.yaml
>>> @@ -0,0 +1,140 @@
>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2
>>> +---
>>> +$id:
>>> +http://devicetree.org/schemas/soc/starfive/starfive,jhb100-syscon.yam
>>> +l#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: StarFive JHB100 SoC system controller
>>> +
>>> +maintainers:
>>> +  - Kevin Xie <kevin.xie at starfivetech.com>
>>> +  - Changhuang Liang <changhuang.liang at starfivetech.com>
>>> +
>>> +description:
>>> +  The StarFive JHB100 SoC system controller provides register
>>> +information such
>>> +  as offset, mask and shift to configure related modules such as PLL and
>> PCIe.
>>
>> How a MMIO based device can provide a MMIO information? What exactly
>> does it provide? Register where the value is the offset of other register?
> 
> For example:
> in per1 syscon:
> offset 0x4 is the register configuration for implementing eMMC extended functions, 
> and offsets 0x40–0x4c are used for PLL7 register configuration.
> 
> In sys0 syscon:
> offsets 0x0–0x2c are used for register configuration of PLL2 to PLL5, 
> and offset 0x38 is used for register configuration to provide the product ID.

That's not what the text said. You wrote the device, in MMIO registers,
provides information: offset, mask and shift.


Best regards,
Krzysztof