[RFC PATCH 1/1] dt-bindings: iommu: riscv: Add bindings for Tenstorrent RISC-V IOMMU

Drew Fustini fustini at kernel.org
Thu Apr 2 13:35:19 PDT 2026


On Wed, Apr 01, 2026 at 11:57:57AM +1030, Joel Stanley wrote:
> On Tue, 10 Mar 2026 at 11:09, Nicholas Piggin <npiggin at gmail.com> wrote:
> >
> > Extend the binding to cover details specific to the Tenstorrent RISC-V
> > IOMMU. In particular, a second register range is added which contains
> > M-privileged registers, e.g., PMAs and PMPs.
> >
> > The RISC-V spec S-privileged registers remain in the first register
> > range and are compatible with "riscv,iommu" so the Linux driver does not
> > notice any difference, but the binding will be used by OpenSBI and
> > potentially other M-mode software.
> >
> > Signed-off-by: Nicholas Piggin <npiggin at gmail.com>
> 
> Reviewed-by: Joel Stanley <joel at jms.id.au>
> 
> Drew, will you take this through the the tt soc tree?

I think it would go through Joerg's iommu tree, but I could if Joerg can
an Ack.

Thanks,
Drew



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