[PATCH v1 22/22] riscv: dts: starfive: jhb100: Add clocks and resets nodes
Changhuang Liang
changhuang.liang at starfivetech.com
Thu Apr 2 03:55:23 PDT 2026
Add clocks and resets nodes for JHB100 RISC-V BMC SoC. They contain
sys0crg/sys1crg/sys2crg/per0crg/per1crg/per2crg/per3crg.
Signed-off-by: Changhuang Liang <changhuang.liang at starfivetech.com>
---
arch/riscv/boot/dts/starfive/jhb100.dtsi | 198 ++++++++++++++++++++++-
1 file changed, 195 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/boot/dts/starfive/jhb100.dtsi b/arch/riscv/boot/dts/starfive/jhb100.dtsi
index 4d03470f78ab..700d00f800bc 100644
--- a/arch/riscv/boot/dts/starfive/jhb100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jhb100.dtsi
@@ -4,6 +4,8 @@
*/
/dts-v1/;
+#include <dt-bindings/clock/starfive,jhb100-crg.h>
+#include <dt-bindings/reset/starfive,jhb100-crg.h>
/ {
compatible = "starfive,jhb100";
@@ -268,12 +270,96 @@ pmu {
<0x00 0x22 0xFFFFFFFF 0xFFFFFF22 0x00007FF8>; /* Event ID 34 */
};
- clk_uart: clk-uart {
- compatible = "fixed-clock"; /* Initial clock handler for UART */
+ osc: osc {
+ compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
+ pll0: pll0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2400000000>;
+ };
+
+ pll1: pll1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1000000000>;
+ };
+
+ pll2: pll2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <903168000>;
+ };
+
+ pll4: pll4 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100700000>;
+ };
+
+ pll5: pll5 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100700000>;
+ };
+
+ pll6: pll6 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2400000000>;
+ };
+
+ pll7: pll7 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1950000000>;
+ };
+
+ per2_gmac2_rgmii_rx: per2-gmac2-rgmii-rx {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ per2_gmac2_rmii_ref: per2-gmac2-rmii-ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
+
+ per2_gmac3_sgmii_tx: per2-gmac3-sgmii-tx {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ per2_gmac3_sgmii_rx: per2-gmac3-sgmii-rx {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ per3_gmac0_rmii_rclki: per3-gmac0-rmii-rclki {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
+
+ per3_gmac1_sgmii_tx: per3-gmac1-sgmii-tx {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ per3_gmac1_sgmii_rx: per3-gmac1-sgmii-rx {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
@@ -315,12 +401,118 @@ bus_nioc: bus_nioc {
uart6: serial at 11982000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x11982000 0x0 0x400>;
- clocks = <&clk_uart>, <&clk_uart>;
+ clocks = <&per0crg JHB100_PER0CLK_SCLK_UART6>,
+ <&per0crg JHB100_PER0CLK_APB_UART6>;
clock-names = "baudclk", "apb_pclk";
+ resets = <&per0crg JHB100_PER0RST_MAIN_RSTN_UART6>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
+
+ per0crg: clock-controller at 11a08000 {
+ compatible = "starfive,jhb100-per0crg";
+ reg = <0x0 0x11a08000 0x0 0x1000>;
+ clocks = <&osc>, <&pll6>,
+ <&sys0crg JHB100_SYS0CLK_BMCPER0_400>,
+ <&sys0crg JHB100_SYS0CLK_BMCPER0_800>,
+ <&sys0crg JHB100_SYS0CLK_BMCPER0_600>,
+ <&sys2crg JHB100_SYS2CLK_BMCPER0_200>;
+ clock-names = "osc", "pll6", "per0_400",
+ "per0_800", "per0_600",
+ "per0_200_init";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ per1crg: clock-controller at 11b40000 {
+ compatible = "starfive,jhb100-per1crg";
+ reg = <0x0 0x11b40000 0x0 0x1000>;
+ clocks = <&pll7>,
+ <&sys0crg JHB100_SYS0CLK_BMCPER1_600>,
+ <&sys0crg JHB100_SYS0CLK_BMCPER1_800>,
+ <&sys2crg JHB100_SYS2CLK_BMCPER1_200>,
+ <&sys2crg JHB100_SYS2CLK_BMCPER1_143>;
+ clock-names = "pll7", "per1_600",
+ "per1_800", "per1_200",
+ "per1_143";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ per2crg: clock-controller at 11bc0000 {
+ compatible = "starfive,jhb100-per2crg";
+ reg = <0x0 0x11bc0000 0x0 0x1000>;
+ clocks = <&sys0crg JHB100_SYS0CLK_BMCPER2_600>,
+ <&sys0crg JHB100_SYS0CLK_BMCPER2_400>,
+ <&sys0crg JHB100_SYS0CLK_BMCPER2_125>,
+ <&per2_gmac2_rgmii_rx>,
+ <&per2_gmac2_rmii_ref>,
+ <&per2_gmac3_sgmii_tx>,
+ <&per2_gmac3_sgmii_rx>,
+ <&osc>;
+ clock-names = "per2_600", "per2_400", "per2_125",
+ "per2_gmac2_rgmii_rx",
+ "per2_gmac2_rmii_ref",
+ "per2_gmac3_sgmii_tx",
+ "per2_gmac3_sgmii_rx",
+ "osc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ per3crg: clock-controller at 11c40000 {
+ compatible = "starfive,jhb100-per3crg";
+ reg = <0x0 0x11c40000 0x0 0x1000>;
+ clocks = <&sys0crg JHB100_SYS0CLK_BMCPER3_600>,
+ <&sys1crg JHB100_SYS1CLK_BMCPER3_100>,
+ <&sys1crg JHB100_SYS1CLK_BMCPER3_125>,
+ <&per3_gmac0_rmii_rclki>,
+ <&per3_gmac1_sgmii_tx>,
+ <&per3_gmac1_sgmii_rx>,
+ <&osc>;
+ clock-names = "per3_600", "per3_100", "per3_125",
+ "per3_gmac0_rmii_rclki",
+ "per3_gmac1_sgmii_tx",
+ "per3_gmac1_sgmii_rx",
+ "osc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ sys0crg: clock-controller at 13000000 {
+ compatible = "starfive,jhb100-sys0crg";
+ reg = <0x0 0x13000000 0x0 0x4000>;
+ clocks = <&osc>, <&pll0>, <&pll1>,
+ <&pll2>;
+ clock-names = "osc", "pll0", "pll1", "pll2";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ sys1crg: clock-controller at 13004000 {
+ compatible = "starfive,jhb100-sys1crg";
+ reg = <0x0 0x13004000 0x0 0x4000>;
+ clocks = <&osc>, <&pll0>, <&pll1>,
+ <&pll2>, <&pll4>, <&pll5>,
+ <&sys0crg JHB100_SYS0CLK_NPU_600>;
+ clock-names = "osc", "pll0", "pll1", "pll2",
+ "pll4", "pll5", "sys1_npu_600";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ sys2crg: clock-controller at 13008000 {
+ compatible = "starfive,jhb100-sys2crg";
+ reg = <0x0 0x13008000 0x0 0x4000>;
+ clocks = <&osc>, <&pll1>,
+ <&sys0crg JHB100_SYS0CLK_GPU0_600>,
+ <&sys0crg JHB100_SYS0CLK_GPU1_600>;
+ clock-names = "osc", "pll1", "sys2_gpu0_600",
+ "sys2_gpu1_600";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
};
};
};
--
2.25.1
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