[PATCH v1 18/22] clk: starfive: Add StarFive JHB100 Peripheral-2 clock driver
Changhuang Liang
changhuang.liang at starfivetech.com
Thu Apr 2 03:55:19 PDT 2026
Add driver for the StarFive JHB100 Peripheral-2 clock controller.
Signed-off-by: Changhuang Liang <changhuang.liang at starfivetech.com>
---
drivers/clk/starfive/Kconfig | 8 +
drivers/clk/starfive/Makefile | 1 +
.../clk/starfive/clk-starfive-jhb100-per2.c | 232 ++++++++++++++++++
3 files changed, 241 insertions(+)
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-per2.c
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index 72cf314c6cfc..01d6d325dcd0 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -89,6 +89,14 @@ config CLK_STARFIVE_JHB100_PER1
Say yes here to support the peripheral-1 clock controller
on the StarFive JHB100 SoC.
+config CLK_STARFIVE_JHB100_PER2
+ bool "StarFive JHB100 peripheral-2 clock support"
+ depends on CLK_STARFIVE_JHB100_SYS0
+ default ARCH_STARFIVE
+ help
+ Say yes here to support the peripheral-2 clock controller
+ on the StarFive JHB100 SoC.
+
config CLK_STARFIVE_JHB100_SYS0
bool "StarFive JHB100 system-0 clock support"
depends on ARCH_STARFIVE || COMPILE_TEST
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index 51511086a727..044e1942ccfa 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_PER0) += clk-starfive-jhb100-per0.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_PER1) += clk-starfive-jhb100-per1.o
+obj-$(CONFIG_CLK_STARFIVE_JHB100_PER2) += clk-starfive-jhb100-per2.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) += clk-starfive-jhb100-sys0.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS1) += clk-starfive-jhb100-sys1.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS2) += clk-starfive-jhb100-sys2.o
diff --git a/drivers/clk/starfive/clk-starfive-jhb100-per2.c b/drivers/clk/starfive/clk-starfive-jhb100-per2.c
new file mode 100644
index 000000000000..42b9dbd11618
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jhb100-per2.c
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JHB100 Peripheral-2 Clock Driver
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ *
+ * Author: Changhuang Liang <changhuang.liang at starfivetech.com>
+ *
+ */
+
+#include <dt-bindings/clock/starfive,jhb100-crg.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+
+#include "clk-starfive-jhb100.h"
+
+#define JHB100_PER2CLK_NUM_CLKS (JHB100_PER2CLK_MAIN_ICG_EN_GMAC3 + 1)
+
+/* external clocks */
+#define JHB100_PER2CLK_600 (JHB100_PER2CLK_NUM_CLKS + 0)
+#define JHB100_PER2CLK_400 (JHB100_PER2CLK_NUM_CLKS + 1)
+#define JHB100_PER2CLK_125 (JHB100_PER2CLK_NUM_CLKS + 2)
+#define JHB100_PER2CLK_GMAC2_RGMII_RX (JHB100_PER2CLK_NUM_CLKS + 3)
+#define JHB100_PER2CLK_GMAC2_RMII_REF (JHB100_PER2CLK_NUM_CLKS + 4)
+#define JHB100_PER2CLK_OSC (JHB100_PER2CLK_NUM_CLKS + 5)
+#define JHB100_PER2CLK_GMAC3_SGMII_TX (JHB100_PER2CLK_NUM_CLKS + 6)
+#define JHB100_PER2CLK_GMAC3_SGMII_RX (JHB100_PER2CLK_NUM_CLKS + 7)
+
+static const struct starfive_clk_data jhb100_per2crg_clk_data[] = {
+ STARFIVE__DIV(JHB100_PER2CLK_300, "per2_300", 2,
+ JHB100_PER2CLK_600),
+ STARFIVE__DIV(JHB100_PER2CLK_100, "per2_100", 4,
+ JHB100_PER2CLK_400),
+ STARFIVE__DIV(JHB100_PER2CLK_50, "per2_50", 2,
+ JHB100_PER2CLK_100),
+ STARFIVE__DIV(JHB100_PER2CLK_GMAC2_RMII_50, "gmac2_rmii_50", 2,
+ JHB100_PER2CLK_100),
+ STARFIVE__DIV(JHB100_PER2CLK_CAN0_CORE_DIV, "can0_core_div", 20,
+ JHB100_PER2CLK_400),
+ STARFIVE__DIV(JHB100_PER2CLK_CAN1_CORE_DIV, "can1_core_div", 20,
+ JHB100_PER2CLK_400),
+ STARFIVE__DIV(JHB100_PER2CLK_CAN0_TIMER, "can0_timer", 100,
+ JHB100_PER2CLK_100),
+ STARFIVE__DIV(JHB100_PER2CLK_CAN1_TIMER, "can1_timer", 100,
+ JHB100_PER2CLK_100),
+ STARFIVE__DIV(JHB100_PER2CLK_RTC_CORE_DIV, "rtc_core_div", 763,
+ JHB100_PER2CLK_OSC),
+ STARFIVE__MUX(JHB100_PER2CLK_GMAC2_RMII_MUX_DLY, "gmac2_rmii_mux_dly", 0, 2,
+ JHB100_PER2CLK_GMAC2_RMII_REF,
+ JHB100_PER2CLK_GMAC2_RMII_50),
+ STARFIVE__DIV(JHB100_PER2CLK_GMAC2_RMII_DIV, "gmac2_rmii_div", 20,
+ JHB100_PER2CLK_GMAC2_RMII_MUX_DLY),
+ STARFIVE__MUX(JHB100_PER2CLK_GMAC2_RGMII_125_MUX, "gmac2_rgmii_125_mux", 0, 2,
+ JHB100_PER2CLK_GMAC2_RGMII_RX,
+ JHB100_PER2CLK_125),
+ STARFIVE__DIV(JHB100_PER2CLK_GMAC2_RGMII_DIV, "gmac2_rgmii_div", 50,
+ JHB100_PER2CLK_125),
+ STARFIVE__MUX(JHB100_PER2CLK_GMAC2_TX_MUX, "gmac2_tx_mux", 0, 2,
+ JHB100_PER2CLK_GMAC2_RMII_DIV,
+ JHB100_PER2CLK_GMAC2_RGMII_DIV),
+ STARFIVE__INV(JHB100_PER2CLK_GMAC2_TX_180_BUF, "gmac2_tx_180_buf",
+ JHB100_PER2CLK_GMAC2_TX_MUX),
+ STARFIVE__MUX(JHB100_PER2CLK_GMAC2_RX_MUX_DLY, "gmac2_rx_mux_dly", 0, 2,
+ JHB100_PER2CLK_GMAC2_RMII_DIV,
+ JHB100_PER2CLK_GMAC2_RGMII_125_MUX),
+ STARFIVE__INV(JHB100_PER2CLK_GMAC2_RX_180_BUF, "gmac2_rx_180_buf",
+ JHB100_PER2CLK_GMAC2_RX_MUX_DLY),
+ STARFIVE__MUX(JHB100_PER2CLK_GMAC2_TXCK_MUX_DLY, "gmac2_txck_mux_dly", 0, 2,
+ JHB100_PER2CLK_GMAC2_RMII_50,
+ JHB100_PER2CLK_GMAC2_TX_MUX),
+ STARFIVE__MUX(JHB100_PER2CLK_GMAC3_TX_125_MUX, "gmac3_tx_125_mux", 0, 2,
+ JHB100_PER2CLK_GMAC3_SGMII_TX,
+ JHB100_PER2CLK_125),
+ STARFIVE__MUX(JHB100_PER2CLK_GMAC3_RX_125_MUX, "gmac3_rx_125_mux", 0, 2,
+ JHB100_PER2CLK_GMAC3_SGMII_RX,
+ JHB100_PER2CLK_125),
+ STARFIVE__DIV(JHB100_PER2CLK_GMAC3_TX_DIV, "gmac3_tx_div", 50,
+ JHB100_PER2CLK_GMAC3_TX_125_MUX),
+ STARFIVE__DIV(JHB100_PER2CLK_GMAC3_RX_DIV, "gmac3_rx_div", 50,
+ JHB100_PER2CLK_GMAC3_RX_125_MUX),
+ STARFIVE_GATE(JHB100_PER2CLK_SENSORS_PERIPH2, "sensors_periph2", 0,
+ JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_FAN_TACH_PCLK, "fan_tach_pclk", 0,
+ JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_TX_I, "ether0_rmiiandrgmii_tx_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC2_TX_MUX),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_RX_I, "ether0_rmiiandrgmii_rx_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC2_RX_MUX_DLY),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_TX_180_I, "ether0_rmiiandrgmii_tx_180_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC2_TX_180_BUF),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_RX_180_I, "ether0_rmiiandrgmii_rx_180_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC2_RX_180_BUF),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_PTP_REF_I, "ether0_rmiiandrgmii_ptp_ref_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_50),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_RMII_I, "ether0_rmiiandrgmii_rmii_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC2_RMII_MUX_DLY),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_CSR_I, "ether0_rmiiandrgmii_csr_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER0_RMIIANDRGMII_ACLK_I, "ether0_rmiiandrgmii_aclk_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_300),
+ STARFIVE_GATE(JHB100_PER2CLK_RMIIANDRGMII_IOMUX_GMAC2_TXCK, "rmiiandrgmii_iomux_gmac2_txck",
+ CLK_IS_CRITICAL, JHB100_PER2CLK_GMAC2_TXCK_MUX_DLY),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER1_SGMII_TX_I, "ether1_sgmii_tx_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC3_TX_DIV),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER1_SGMII_RX_I, "ether1_sgmii_rx_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC3_RX_DIV),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER1_SGMII_TX_125_I, "ether1_sgmii_tx_125_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC3_TX_125_MUX),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER1_SGMII_RX_125_I, "ether1_sgmii_rx_125_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_GMAC3_RX_125_MUX),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER1_SGMII_PTP_REF_I, "ether1_sgmii_ptp_ref_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_50),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER1_SGMII_CSR_I, "ether1_sgmii_csr_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER1_SGMII_ACLK_I, "ether1_sgmii_aclk_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_300),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER1_SGMII_PHY_PCLK_I, "ether1_sgmii_phy_pclk_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_ETHER1_SGMII_REF_25_I, "ether1_sgmii_ref_25_i",
+ CLK_IGNORE_UNUSED, JHB100_PER2CLK_OSC),
+ STARFIVE_GATE(JHB100_PER2CLK_MAIN_ICG_EN_CAN0, "main_icg_en_can0", 0,
+ JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_MAIN_ICG_EN_CAN1, "main_icg_en_can1", 0,
+ JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_MAIN_ICG_EN_DMAC_8CH, "main_icg_en_dmac_8ch", 0,
+ JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_MAIN_ICG_EN_RTC_SCAN, "main_icg_en_rtc_scan", CLK_IS_CRITICAL,
+ JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_MAIN_ICG_EN_ADC0, "main_icg_en_adc0", 0,
+ JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_MAIN_ICG_EN_ADC1, "main_icg_en_adc1", 0,
+ JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_MAIN_ICG_EN_GMAC2, "main_icg_en_gmac2", 0,
+ JHB100_PER2CLK_100),
+ STARFIVE_GATE(JHB100_PER2CLK_MAIN_ICG_EN_GMAC3, "main_icg_en_gmac3", 0,
+ JHB100_PER2CLK_100),
+};
+
+static int jhb100_per2crg_probe(struct platform_device *pdev)
+{
+ struct starfive_clk_priv *priv;
+ unsigned int idx;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev,
+ struct_size(priv, reg, JHB100_PER2CLK_NUM_CLKS),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ spin_lock_init(&priv->rmw_lock);
+ priv->num_reg = JHB100_PER2CLK_NUM_CLKS;
+ priv->dev = &pdev->dev;
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ for (idx = 0; idx < JHB100_PER2CLK_NUM_CLKS; idx++) {
+ u32 max = jhb100_per2crg_clk_data[idx].max;
+ struct clk_parent_data parents[4] = {};
+ struct clk_init_data init = {
+ .name = jhb100_per2crg_clk_data[idx].name,
+ .ops = starfive_clk_ops(max),
+ .parent_data = parents,
+ .num_parents =
+ ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1,
+ .flags = jhb100_per2crg_clk_data[idx].flags,
+ };
+ struct starfive_clk *clk = &priv->reg[idx];
+ unsigned int i;
+
+ if (!init.name)
+ continue;
+
+ for (i = 0; i < init.num_parents; i++) {
+ unsigned int pidx = jhb100_per2crg_clk_data[idx].parents[i];
+
+ if (pidx < JHB100_PER2CLK_NUM_CLKS)
+ parents[i].hw = &priv->reg[pidx].hw;
+ else if (pidx == JHB100_PER2CLK_600)
+ parents[i].fw_name = "per2_600";
+ else if (pidx == JHB100_PER2CLK_400)
+ parents[i].fw_name = "per2_400";
+ else if (pidx == JHB100_PER2CLK_125)
+ parents[i].fw_name = "per2_125";
+ else if (pidx == JHB100_PER2CLK_GMAC2_RGMII_RX)
+ parents[i].fw_name = "per2_gmac2_rgmii_rx";
+ else if (pidx == JHB100_PER2CLK_GMAC2_RMII_REF)
+ parents[i].fw_name = "per2_gmac2_rmii_ref";
+ else if (pidx == JHB100_PER2CLK_GMAC3_SGMII_TX)
+ parents[i].fw_name = "per2_gmac3_sgmii_tx";
+ else if (pidx == JHB100_PER2CLK_GMAC3_SGMII_RX)
+ parents[i].fw_name = "per2_gmac3_sgmii_rx";
+ else if (pidx == JHB100_PER2CLK_OSC)
+ parents[i].fw_name = "osc";
+ }
+
+ clk->hw.init = &init;
+ clk->idx = idx;
+ clk->max_div = max & STARFIVE_CLK_DIV_MASK;
+
+ ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
+ if (ret)
+ return ret;
+ }
+
+ ret = devm_of_clk_add_hw_provider(&pdev->dev, starfive_clk_get, priv);
+ if (ret)
+ return ret;
+
+ return jhb100_reset_controller_register(priv, "r-per2", 0);
+}
+
+static const struct of_device_id jhb100_per2crg_match[] = {
+ { .compatible = "starfive,jhb100-per2crg" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_per2crg_match);
+
+static struct platform_driver jhb100_per2crg_driver = {
+ .probe = jhb100_per2crg_probe,
+ .driver = {
+ .name = "clk-starfive-jhb100-per2",
+ .of_match_table = jhb100_per2crg_match,
+ },
+};
+module_platform_driver(jhb100_per2crg_driver);
+
+MODULE_AUTHOR("Changhuang Liang <changhuang.liang at starfivetech.com>");
+MODULE_DESCRIPTION("StarFive JHB100 Peripheral-2 Clock Driver");
+MODULE_LICENSE("GPL");
--
2.25.1
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