[PATCH v3 3/3] riscv: dts: spacemit: define a SPI controller node

[Troy Mitchell]

On Tue, Sep 23, 2025 at 02:31:31PM +0800, Junhui Liu wrote:
> Hi Troy,
> 
> On 9/23/25 10:59 AM, Troy Mitchell wrote:
> > On Tue, Sep 23, 2025 at 08:19:30AM +0800, Yixun Lan wrote:
> > > Hi Alex,
> > > 
> > > On 11:17 Mon 22 Sep     , Alex Elder wrote:
> > > > Define a node for the fourth SoC SPI controller (number 3) on
> > > > the SpacemiT K1 SoC.
> > > > 
> > > > Enable it on the Banana Pi BPI-F3 board, which exposes this feature
> > > > via its GPIO block:
> > > >    GPIO PIN 19:  MOSI
> > > >    GPIO PIN 21:  MISO
> > > >    GPIO PIN 23:  SCLK
> > > >    GPIO PIN 24:  SS (inverted)
> > > > 
> > > > Define pincontrol configurations for the pins as used on that board.
> > > > 
> > > > (This was tested using a GigaDevice GD25Q64E SPI NOR chip.)
> > > > 
> > > > Signed-off-by: Alex Elder <elder at riscstar.com>
> > > > ---
> > > > v3: - Moved the SPI controller into the dma-bus memory region
> > > > 
> > > >   .../boot/dts/spacemit/k1-bananapi-f3.dts      |  7 +++++++
> > > >   arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi  | 20 +++++++++++++++++++
> > > >   arch/riscv/boot/dts/spacemit/k1.dtsi          | 16 +++++++++++++++
> > > >   3 files changed, 43 insertions(+)
> > > > 
> > > > diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
> > > > index 2aaaff77831e1..d9d865fbe320e 100644
> > > > --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
> > > > +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
> > > > @@ -14,6 +14,7 @@ aliases {
> > > >   		ethernet0 = &eth0;
> > > >   		ethernet1 = &eth1;
> > > >   		serial0 = &uart0;
> > > > +		spi3 = &spi3;
> > > >   	};
> > > >   	chosen {
> > > > @@ -92,6 +93,12 @@ &pdma {
> > > >   	status = "okay";
> > > >   };
> > > > +&spi3 {
> > > > +	pinctrl-0 = <&ssp3_0_cfg>;
> > > > +	pinctrl-names = "default";
> > > > +	status = "okay";
> > > > +};
> > > > +
> > > >   &uart0 {
> > > >   	pinctrl-names = "default";
> > > >   	pinctrl-0 = <&uart0_2_cfg>;
> > > > diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
> > > > index aff19c86d5ff3..205c201a3005c 100644
> > > > --- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
> > > > +++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
> > > > @@ -76,4 +76,24 @@ pwm14-1-pins {
> > > >   			drive-strength = <32>;
> > > >   		};
> > > >   	};
> > > > +
> > > > +	ssp3_0_cfg: ssp3-0-cfg {
> > > ..
> > > > +		ssp3-0-no-pull-pins {
> > > I'd prefer not to enforce "pull" info inside the name, you can't embed
> > > all property info, besides, what's if you want to change/override later?
> > > 
> > > how about just name it as ssp3-0-defaul-pins or simply ssp3-0-pins?
> > uart: uart0_2_cfg and function is 2.
> > pwm: pwm14_1_cfg and function is 4
> > spi: ssp3_0_cfg and function is 2
> > 
> > I’m a bit confused about the meaning of the second number here.
> > Is it intended to be an index, or the function number?
> > 
> > If it’s an index, should it start from 0 or 1?
> > The starting point seems inconsistent across pwm/spi/uart.
> > If it’s supposed to be the function number,
> > then the spi and pwm parts look incorrect.
> > 
> > Could you clarify this? Yixun.
> 
> I think the second number represents the index of the pin group available
> for this device.
> 
> Take pwm14 as an example: according to the manual, the first pin group
> (index 0) available for pwm14 is GPIO6 with function 3, while the second
> group (index 1) is GPIO44 with function 4.
Thanks. Junhui.
with the hints from you and Alex, it’s now much clearer to me.

                    - Troy
> 
> >                  - Troy
> 
> -- 
> Best regards,
> Junhui Liu
> 
>