[External] Re: [PATCH v2 0/4] riscv: Add Zalasr ISA extension support

[Xu Lu]

Hi Andrea,

On Fri, Sep 19, 2025 at 3:45 PM Andrea Parri <parri.andrea at gmail.com> wrote:
>
> > The existing implementation of spin_unlock, when followed by
> > spin_lock, is equal to 'FENCE rw, rw' for operations before
>
> This is not true without Zacas, that is, when using LR/SC: write-to-read
> remains unordered in that case.

Yes. Thanks for your corrections.

The LR/SC here, when Zacas or Zabha is not implemented, will behaves like:

    fence rw, w
    sd
    lr.w
    sc,w
    fence r, rw

The 'fence rw, w' ensures the order of operations before itself and 'sc.w'.
The 'fence r, rw' ensures the order of operations after itself and 'lr.w'.
The operations between 'lr.w' and 'sc.w' are as few as possible and
cannot contain load or stores as is said in section 13.3 of riscv
unpriv spec:
"The dynamic code executed between the LR and SC instructions can only
contain instructions from the base ''I'' instruction set, excluding
loads, stores, backward jumps, taken backward branches, JALR, FENCE,
and SYSTEM instructions."

So in summary, though it does not provide 'fence rw, rw' semantics,
there is limited space available for the CPU to reorder.

And, still, I think calling spin_unlock immediately followed by
spin_lock on the same core is much rarer than calling spin_unlock on
one core and spin_lock on another core.

Best regards,
Xu Lu

>
>   Andrea