[PATCH v1 1/3] iommu/riscv: Add iommu perf driver

[guoyaxing at bosc.ac.cn]

Hi, Will


From: Will Deacon



Date: 2025-09-15 18:38



To: Yaxing Guo



CC: linux-riscv; iommu; tjeznach; joro; robin.murphy; paul.walmsley; palmer; aou; alex; anxu; wangran



Subject: Re: [PATCH v1 1/3] iommu/riscv: Add iommu perf driver



On Mon, Sep 15, 2025 at 10:09:09AM +0800, Yaxing Guo wrote:



>> This patch introduces a performance monitor driver for RISC-V IOMMU



>> iohpm implementions that support hardware performance counters.



>> The driver expose RISC-V-IOMMU-specific performance events (eg. cycles,



>> tlb miss ...)through the Linux perf subsystem, enabling developers



>> to profile and optimize I/O translation performance.



>>



>> Key features:



>> - Implements a perf PMU driver for RISC-V IOMMU.



>>



>> - Exposes IOMMU perf events, such as 'cycles', 'tlb_miss'... via



>>   /sys/devices/riscv-iommu-pmu/events/, allowing use with perf



>>   tools:



>>     perf stat -C 0 -e riscv-iommu-pmu/cycles/ ...



>>     perf stat -C 0 -e riscv-iommu-pmu/tlb_miss/ ...



>>     ...



>> - Supports event filtering through configureable attributes exposed



>>   in /sys/devices/riscv-iommu-pmu/format/, including:



>>   dv_gscv, pv_pscv，did_gscid，pid_pscid，idt (riscv iommu spec 5-23).



>>



>> - Implements overflow interrupt handling.



>>



>> - Adds device tree binding support via optional 'pmu-name' property



>>   allowing platform-specific IOMMU implementations to specify a custom



>>   defined event ID list. If not provided, the driver defaults to only



>>   supporting 'cycles'. When set to 'dummy', it enables all 9 standard



>>   event IDs as defined in riscv iommu spec(5-23).



>>



>> Signed-off-by: Yaxing Guo <guoyaxing at bosc.ac.cn>



>> ---



>>  drivers/iommu/riscv/iommu-perf.c | 535 +++++++++++++++++++++++++++++++



>>  drivers/iommu/riscv/iommu-perf.h |  88 +++++



>>  drivers/iommu/riscv/iommu.h      |   8 +



>>  3 files changed, 631 insertions(+)



>>  create mode 100644 drivers/iommu/riscv/iommu-perf.c



>>  create mode 100644 drivers/iommu/riscv/iommu-perf.h



 



> PMU drivers are better placed under drivers/perf/



 



> (the Arm SMMUv3 PMU driver lives there, for example).



I did a quick reading of SMMU pmu driver in drivers/perf/.  However, If the RISC-V IOMMU PMU driver is placed under drivers/perf/ as the SMMU did, it would cause an overlap in the iomem resource region between the two devices(iommu & iommu pmu), because it needs to share interrupt-related registers (such as the IPSR register) with the main IOMMU driver.

Yaxing Guo


> Will