[PATCH 6/7] riscv: dts: Add Tenstorrent Blackhole A0 SoC PCIe cards

[Conor Dooley]

On Sat, Sep 13, 2025 at 02:31:05PM -0700, Drew Fustini wrote:
> new file mode 100644
> index 0000000000000000000000000000000000000000..b2b08023643a2cebd4f924579024290bb355c9b3
> --- /dev/null
> +++ b/arch/riscv/boot/dts/tenstorrent/blackhole-a0-card.dts
> @@ -0,0 +1,14 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/dts-v1/;
> +
> +#include "blackhole-a0.dtsi"
> +
> +/ {
> +	model = "Tenstorrent Blackhole A0 SoC PCIe card";
> +	compatible = "tenstorrent,blackhole-a0-card", "tenstorrent,blackhole-a0";
> +
> +	memory at 0 {
> +		device_type = "memory";
> +		reg = <0x4000 0x30000000 0x1 0x00000000>;

This isn't at address zero as the node address claims.

> +	};
> +};
> diff --git a/arch/riscv/boot/dts/tenstorrent/blackhole-a0.dtsi b/arch/riscv/boot/dts/tenstorrent/blackhole-a0.dtsi
> new file mode 100644
> index 0000000000000000000000000000000000000000..517b6442ff0fe61659069e29318ad3f01bc504e2
> --- /dev/null
> +++ b/arch/riscv/boot/dts/tenstorrent/blackhole-a0.dtsi
> @@ -0,0 +1,112 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +// Copyright 2025 Tenstorrent AI ULC
> +/dts-v1/;
> +
> +/ {
> +	compatible = "tenstorrent,blackhole-a0";
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	cpus {
> +		#address-cells = <0x1>;
> +		#size-cells = <0x0>;
> +		timebase-frequency = <50000000>;
> +
> +		cpu at 0 {
> +			compatible = "sifive,x280", "sifive,rocket0", "riscv";
> +			device_type = "cpu";
> +			reg = <0>;
> +			mmu-type = "riscv,sv57";

> +			riscv,isa = "rv64imafdcv_zicsr_zifencei_zfh_zba_zbb_sscofpmf";

What's the benefit of retaining this property?

> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
> +					       "zifencei", "zfh", "zba", "zbb", "sscofpmf";
> +			riscv,cboz-block-size = <0x40>;

cboz block size, but no zicboz in your extensions list?
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