[RFC PATCH] kvm/riscv: Add ctxsstatus and ctxhstatus for migration

[Jinyu Tang]

When migrating a VM which guest running in user mode 
(e.g., executing a while(1) application), the target 
VM fails to run because it loses the information of 
guest_context.hstatus and guest_context.sstatus. The 
VM uses the initialized values instead of the correct ones.

This patch adds two new context registers (ctxsstatus and 
ctxhstatus) to the kvm_vcpu_csr structure and implements 
the necessary KVM get and set logic to preserve these values 
during migration.

QEMU needs to be updated to support these new registers.
See https://github.com/tjy-zhu/qemu
for the corresponding QEMU changes.

I'm not sure if adding these CSR registers is a right way. RISCV
KVM doesn't have API to save these two context csrs now. I will
submit the corresponding QEMU patch to the QEMU community if
KVM has API to get and set them.

Signed-off-by: Jinyu Tang <tjytimi at 163.com>
Tested-by: Tianshun Sun <stsmail163 at 163.com>
---
 arch/riscv/include/asm/kvm_host.h |  2 ++
 arch/riscv/include/uapi/asm/kvm.h |  2 ++
 arch/riscv/kvm/vcpu_onereg.c      | 16 ++++++++++++++++
 3 files changed, 20 insertions(+)

diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
index d71d3299a..55604b075 100644
--- a/arch/riscv/include/asm/kvm_host.h
+++ b/arch/riscv/include/asm/kvm_host.h
@@ -161,6 +161,8 @@ struct kvm_vcpu_csr {
 	unsigned long vsatp;
 	unsigned long scounteren;
 	unsigned long senvcfg;
+	unsigned long ctxsstatus;
+	unsigned long ctxhstatus;
 };
 
 struct kvm_vcpu_config {
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index ef27d4289..cd7d7087f 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -81,6 +81,8 @@ struct kvm_riscv_csr {
 	unsigned long satp;
 	unsigned long scounteren;
 	unsigned long senvcfg;
+	unsigned long ctxsstatus;
+	unsigned long ctxhstatus;
 };
 
 /* AIA CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
index cce6a38ea..284ee6e81 100644
--- a/arch/riscv/kvm/vcpu_onereg.c
+++ b/arch/riscv/kvm/vcpu_onereg.c
@@ -489,6 +489,12 @@ static int kvm_riscv_vcpu_general_get_csr(struct kvm_vcpu *vcpu,
 	if (reg_num >= sizeof(struct kvm_riscv_csr) / sizeof(unsigned long))
 		return -ENOENT;
 
+	if (reg_num == KVM_REG_RISCV_CSR_REG(ctxsstatus))
+		csr->ctxsstatus = vcpu->arch.guest_context.sstatus;
+
+	if (reg_num == KVM_REG_RISCV_CSR_REG(ctxhstatus))
+		csr->ctxhstatus = vcpu->arch.guest_context.hstatus;
+
 	if (reg_num == KVM_REG_RISCV_CSR_REG(sip)) {
 		kvm_riscv_vcpu_flush_interrupts(vcpu);
 		*out_val = (csr->hvip >> VSIP_TO_HVIP_SHIFT) & VSIP_VALID_MASK;
@@ -515,6 +521,16 @@ static int kvm_riscv_vcpu_general_set_csr(struct kvm_vcpu *vcpu,
 
 	((unsigned long *)csr)[reg_num] = reg_val;
 
+	if (reg_num == KVM_REG_RISCV_CSR_REG(ctxsstatus)) {
+		if (csr->ctxsstatus != 0)
+			vcpu->arch.guest_context.sstatus = csr->ctxsstatus;
+	}
+
+	if (reg_num == KVM_REG_RISCV_CSR_REG(ctxhstatus)) {
+		if (csr->ctxhstatus != 0)
+			vcpu->arch.guest_context.hstatus = csr->ctxhstatus;
+	}
+
 	if (reg_num == KVM_REG_RISCV_CSR_REG(sip))
 		WRITE_ONCE(vcpu->arch.irqs_pending_mask[0], 0);
 
-- 
2.43.0