[PATCH 3/6] dt-bindings: phy: spacemit: introduce PCIe root complex

[Manivannan Sadhasivam]

On Wed, Aug 13, 2025 at 01:46:57PM GMT, Alex Elder wrote:

Subject should have 'pci' prefix, not 'phy'.

> Add the Device Tree binding for the PCIe root complex found on the
> SpacemiT K1 SoC.  This device is derived from the Synopsys Designware
> PCIe IP.  It supports up to three PCIe ports operating at PCIe gen 2
> link speeds (5 GT/sec).  One of the ports uses a combo PHY, which is
> typically used to support a USB 3 port.
> 
> Signed-off-by: Alex Elder <elder at riscstar.com>
> ---
>  .../bindings/pci/spacemit,k1-pcie-rc.yaml     | 141 ++++++++++++++++++
>  1 file changed, 141 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/spacemit,k1-pcie-rc.yaml
> 
> diff --git a/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-rc.yaml b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-rc.yaml
> new file mode 100644
> index 0000000000000..6bcca2f91a6fd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-rc.yaml
> @@ -0,0 +1,141 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/spacemit,k1-pcie-rc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: SpacemiT K1 PCI Express Root Complex
> +
> +maintainers:
> +  - Alex Elder <elder at riscstar.com>
> +
> +description:
> +  The SpacemiT K1 SoC PCIe root complex controller is based on the
> +  Synopsys DesignWare PCIe IP.
> +
> +properties:
> +  compatible:
> +    const: spacemit,k1-pcie-rc.yaml
> +
> +  reg:
> +    items:
> +      - description: DesignWare PCIe registers
> +      - description: ATU address space
> +      - description: PCIe configuration space
> +      - description: Link control registers
> +
> +  reg-names:
> +    items:
> +      - const: dbi
> +      - const: atu
> +      - const: config
> +      - const: link
> +
> +  clocks:
> +    items:
> +      - description: DWC PCIe Data Bus Interface (DBI) clock
> +      - description: DWC PCIe application AXI-bus Master interface clock
> +      - description: DWC PCIe application AXI-bus Slave interface clock.
> +
> +  clock-names:
> +    items:
> +      - const: dbi
> +      - const: mstr
> +      - const: slv
> +
> +  resets:
> +    items:
> +      - description: DWC PCIe Data Bus Interface (DBI) reset
> +      - description: DWC PCIe application AXI-bus Master interface reset
> +      - description: DWC PCIe application AXI-bus Slave interface reset.
> +      - description: Global reset; must be deasserted for PHY to function
> +
> +  reset-names:
> +    items:
> +      - const: dbi
> +      - const: mstr
> +      - const: slv
> +      - const: global
> +
> +  interrupts-extended:
> +    maxItems: 1

What is the purpose of this property? Is it for MSI or INTx?

> +
> +  spacemit,syscon-pmu:
> +    description:
> +      PHandle that refers to the APMU system controller, whose
> +      regmap is used in managing resets and link state.
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +
> +  device_type:
> +    const: pci
> +
> +  max-link-speed:
> +    const: 2

Why do you need to limit it to 5 GT/s always?

> +
> +  num-viewport:
> +    const: 8
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - resets
> +  - reset-names
> +  - spacemit,syscon-pmu
> +  - "#address-cells"
> +  - "#size-cells"
> +  - device_type
> +  - max-link-speed

Same comment as above.

> +  - bus-range
> +  - num-viewport
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/spacemit,k1-syscon.h>
> +    pcie0: pcie at ca000000 {
> +        compatible = "spacemit,k1-pcie-rc";
> +        reg = <0x0 0xca000000 0x0 0x00001000>,
> +              <0x0 0xca300000 0x0 0x0001ff24>,
> +              <0x0 0x8f000000 0x0 0x00002000>,
> +              <0x0 0xc0b20000 0x0 0x00001000>;
> +        reg-names = "dbi",
> +                    "atu",
> +                    "config",
> +                    "link";
> +
> +        ranges = <0x01000000 0x8f002000 0x0 0x8f002000 0x0 0x100000>,

I/O port CPU address starts from 0.

- Mani

-- 
மணிவண்ணன் சதாசிவம்