[PATCH v2] iommu/riscv: Fix irq failure due to idx mismatch in icvec

[Yaxing Guo]

In icvec, the idx of civ, fiv, pmiv and piv are 0, 1, 2, 3
(According to spec 5.27). And usually, the interrupt-names
property in dts riscv-iommu node also follows this (In qemu
virt machine follows this) which will cause hardware irq
number errors (Especially when using qemu virt machine to
start Linux).

Fixes: 856c0cfe5c5f ("iommu/riscv: Command and fault queue support")
Signed-off-by: Yaxing Guo <guoyaxing at bosc.ac.cn>
---
Changes in v2:
  - Move the "FIELD_PREP(RISCV_IOMMU_ICVEC_PMIV, 2 % iommu->irqs_count)"
    above of "FIELD_PREP(RISCV_IOMMU_ICVEC_PIV, 3 % iommu->irqs_count)"
  - Add the Fixes tag.

 drivers/iommu/riscv/iommu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c
index 0eae2f4bdc5e..103c2fcd4837 100644
--- a/drivers/iommu/riscv/iommu.c
+++ b/drivers/iommu/riscv/iommu.c
@@ -1584,8 +1584,8 @@ static int riscv_iommu_init_check(struct riscv_iommu_device *iommu)
 		return -EINVAL;
 
 	iommu->icvec = FIELD_PREP(RISCV_IOMMU_ICVEC_FIV, 1 % iommu->irqs_count) |
-		       FIELD_PREP(RISCV_IOMMU_ICVEC_PIV, 2 % iommu->irqs_count) |
-		       FIELD_PREP(RISCV_IOMMU_ICVEC_PMIV, 3 % iommu->irqs_count);
+		       FIELD_PREP(RISCV_IOMMU_ICVEC_PMIV, 2 % iommu->irqs_count) |
+		       FIELD_PREP(RISCV_IOMMU_ICVEC_PIV, 3 % iommu->irqs_count);
 	riscv_iommu_writeq(iommu, RISCV_IOMMU_REG_ICVEC, iommu->icvec);
 	iommu->icvec = riscv_iommu_readq(iommu, RISCV_IOMMU_REG_ICVEC);
 	if (max(max(FIELD_GET(RISCV_IOMMU_ICVEC_CIV, iommu->icvec),
-- 
2.34.1