[PATCH 2/3] riscv: dts: thead: add ziccrse for th1520

[Conor Dooley]

On Fri, Sep 12, 2025 at 02:45:27AM +0800, Han Gao wrote:
> th1520 support Ziccrse ISA extension [1].
> 
> Link: https://lore.kernel.org/all/20241103145153.105097-12-alexghiti@rivosinc.com/ [1]

I don't see what this link has to do with th1520 supporting the
extension. The kernel supporting it has nothing to do with whether it
should be in the dts or not. A useful link would substantiate your
claim.

> Signed-off-by: Han Gao <rabenda.cn at gmail.com>
> Signed-off-by: Han Gao <gaohan at iscas.ac.cn>

You only need to sign this off once.

Cheers,
Conor.

> ---
>  arch/riscv/boot/dts/thead/th1520.dtsi | 24 ++++++++++++++++--------
>  1 file changed, 16 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
> index 59d1927764a6..7f07688aa964 100644
> --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> @@ -24,8 +24,10 @@ c910_0: cpu at 0 {
>  			device_type = "cpu";
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
> -			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> -					       "zifencei", "zihpm", "xtheadvector";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> +					       "ziccrse", "zicntr", "zicsr",
> +					       "zifencei", "zihpm",
> +					       "xtheadvector";
>  			thead,vlenb = <16>;
>  			reg = <0>;
>  			i-cache-block-size = <64>;
> @@ -49,8 +51,10 @@ c910_1: cpu at 1 {
>  			device_type = "cpu";
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
> -			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> -					       "zifencei", "zihpm", "xtheadvector";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> +					       "ziccrse", "zicntr", "zicsr",
> +					       "zifencei", "zihpm",
> +					       "xtheadvector";
>  			thead,vlenb = <16>;
>  			reg = <1>;
>  			i-cache-block-size = <64>;
> @@ -74,8 +78,10 @@ c910_2: cpu at 2 {
>  			device_type = "cpu";
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
> -			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> -					       "zifencei", "zihpm", "xtheadvector";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> +					       "ziccrse", "zicntr", "zicsr",
> +					       "zifencei", "zihpm",
> +					       "xtheadvector";
>  			thead,vlenb = <16>;
>  			reg = <2>;
>  			i-cache-block-size = <64>;
> @@ -99,8 +105,10 @@ c910_3: cpu at 3 {
>  			device_type = "cpu";
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
> -			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> -					       "zifencei", "zihpm", "xtheadvector";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> +					       "ziccrse", "zicntr", "zicsr",
> +					       "zifencei", "zihpm",
> +					       "xtheadvector";
>  			thead,vlenb = <16>;
>  			reg = <3>;
>  			i-cache-block-size = <64>;
> -- 
> 2.47.3
> 
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