[GIT PULL] RISC-V Fixes for 6.17-rc5

[Alexandre Ghiti]

The following changes since commit b320789d6883cc00ac78ce83bccbfe7ed58afcf0:

   Linux 6.17-rc4 (2025-08-31 15:33:07 -0700)

are available in the Git repository at:

   git://git.kernel.org/pub/scm/linux/kernel/git/alexghiti/linux 
tags/riscv-fixes-6.17-rc5

for you to fetch changes up to 1fa00f3deacafe202eba6887deba74ea6402c883:

   riscv: Use an atomic xchg in pudp_huge_get_and_clear() (2025-09-02 
07:34:21 +0000)

----------------------------------------------------------------
riscv fixes for 6.17-rc5

- A fix for a link error by disabling LTO on medlow code model
- 4 fixes where we used xlen-bits wide loads on 32-bit values
- A fix in user access routines where we should have written the size of 
the destination, not the size of the source, which appeared in glibc 
testsuite
- A fix in ACPI riscv csr read routines where the error code was incorrect
- A fix for THP PUD to prevent returning an old pte value

----------------------------------------------------------------
Alexandre Ghiti (1):
       riscv: Use an atomic xchg in pudp_huge_get_and_clear()

Anup Patel (1):
       ACPI: RISC-V: Fix FFH_CPPC_CSR error handling

Aurelien Jarno (1):
       riscv: uaccess: fix __put_user_nocheck for unaligned accesses

Nathan Chancellor (1):
       riscv: Only allow LTO with CMODEL_MEDANY

Radim Krčmář (4):
       riscv: use lw when reading int cpu in new_vmalloc_check
       riscv: use lw when reading int cpu in asm_per_cpu
       riscv, bpf: use lw when reading int cpu in BPF_MOV64_PERCPU_REG
       riscv, bpf: use lw when reading int cpu in bpf_get_smp_processor_id

  arch/riscv/Kconfig               |  2 +-
  arch/riscv/include/asm/asm.h     |  2 +-
  arch/riscv/include/asm/pgtable.h | 11 +++++++++++
  arch/riscv/include/asm/uaccess.h |  2 +-
  arch/riscv/kernel/entry.S        |  2 +-
  arch/riscv/net/bpf_jit_comp64.c  |  4 ++--
  drivers/acpi/riscv/cppc.c        |  4 ++--
  7 files changed, 19 insertions(+), 8 deletions(-)