[PATCH v1 2/2] riscv: Introduce support for hardware break/watchpoints

[Paul Walmsley]

On Thu, 10 Jul 2025, Himanshu Chauhan wrote:

> RISC-V hardware breakpoint framework is built on top of perf subsystem
> and uses SBI debug trigger extension to
> install/uninstall/update/enable/disable hardware triggers as specified
> in Sdtrig ISA extension.
> 
> Signed-off-by: Himanshu Chauhan <hchauhan at ventanamicro.com>

Talking with Anup, it sounds like you're planning an updated version of 
this one, so will hold off on it.


- Paul