[PATCH] riscv: dts: allwinner: d1: fix vlenb property

[Chen-Yu Tsai]

On Wed, 19 Nov 2025 23:35:06 +0300, Sergey Matyukevich wrote:
> According to [1], the C906 vector registers are 128 bits wide.
> The 'thead,vlenb' property specifies the vector register length
> in bytes, so its value must be set to 16.
> 
> [1] https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf
> 
> 
> [...]

Applied to sunxi/fixes-for-6.18 in local tree, thanks!

[1/1] riscv: dts: allwinner: d1: fix vlenb property
      commit: 57c5543b94d0c0280145a4a7445a2c1ae074879e

Best regards,
-- 
Chen-Yu Tsai <wens at kernel.org>