[PATCH v3 00/13] riscv: Add initial support for Anlogic DR1V90

[Conor Dooley]

On Tue, Oct 21, 2025 at 05:41:35PM +0800, Junhui Liu wrote:
> This introduces initial support for the Anlogic DR1V90 SoC [1] and the
> Milianke MLKPAI-FS01 [2] board.
> 
> The DR1V90 is a RISC-V based FPSoC from Anlogic, featuring a Nuclei
> UX900 [3] core as its processing system (PS) and 94,464 LUTs in the
> programmable logic (PL) part. The Milianke MLKPAI-FS01 board is one of
> the first platforms based on this SoC, with UART1 routed to a Type-C
> interface for console access.
> 
> Tested on the Milianke MLKPAI-FS01 board with both the vendor's OpenSBI
> and the not-yet-upstreamed mainline OpenSBI [4], as well as the vendor’s
> U-Boot. Because the vendor’s OpenSBI is loaded at 0x1f300000, we have
> to additionally reserve the DRAM region 0x1fe00000–0x1fffffff to prevent
> overlap if using vendor's OpenSBI.
> 
> Link: https://www.anlogic.com/product/fpga/saldragon/dr1 [1]
> Link: https://www.milianke.com/product-item-104.html [2]
> Link: https://nucleisys.com/product/900.php [3]
> Link: https://github.com/pigmoral/opensbi/tree/dr1v90 [4]

Thanks for grabbing the irqchip stuff Thomas.

I've applied this, with myself listed as maintainer. I set the status to
"Odd Fixes" because I will be doing no work on it and only applying
patches that people send in. I'll happy pass the platform off to someone
qualified to maintain it, should that person be willing to do so :)

Patches are here:
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/log/?h=anlogic-initial

I'll submit as a standalone PR to Arnd et al over in the soc group for
the next release.

Cheers,
Conor.
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