[PATCH 1/3] riscv: soc: re-organized allwinner menu

[Krzysztof Kozlowski]

On 08/11/2025 15:47, Krzysztof Kozlowski wrote:
> On 08/11/2025 14:59, revy wrote:
>>
>>
>>
>>> -----Original Messages-----
>>> From: "Krzysztof Kozlowski" <krzk at kernel.org>
>>> Sent Time: 2025-11-08 19:29:07 (Saturday)
>>> To: gaohan at iscas.ac.cn, "Paul Walmsley" <pjw at kernel.org>, "Palmer Dabbelt" <palmer at dabbelt.com>, "Albert Ou" <aou at eecs.berkeley.edu>, "Alexandre Ghiti" <alex at ghiti.fr>, "Rob Herring" <robh at kernel.org>, "Krzysztof Kozlowski" <krzk+dt at kernel.org>, "Conor Dooley" <conor+dt at kernel.org>, "Chen-Yu Tsai" <wens at csie.org>, "Jernej Skrabec" <jernej.skrabec at gmail.com>, "Samuel Holland" <samuel at sholland.org>, "Yixun Lan" <dlan at gentoo.org>, "Drew Fustini" <fustini at kernel.org>, "Geert Uytterhoeven" <geert+renesas at glider.be>, "Guodong Xu" <guodong at riscstar.com>, "Haylen Chu" <heylenay at 4d2.org>, "Joel Stanley" <joel at jms.id.au>
>>> Cc: linux-riscv at lists.infradead.org, linux-kernel at vger.kernel.org, devicetree at vger.kernel.org, linux-arm-kernel at lists.infradead.org, linux-sunxi at lists.linux.dev, "Han Gao" <rabenda.cn at gmail.com>
>>> Subject: Re: [PATCH 1/3] riscv: soc: re-organized allwinner menu
>>>
>>> On 08/11/2025 09:20, gaohan at iscas.ac.cn wrote:
>>>> From: Han Gao <gaohan at iscas.ac.cn>
>>>>
>>>> Allwinner currently offers d1(s)/v821/v861/v881 on RISC-V,
>>>> using different IPs.
>>>>
>>>> d1(s): Xuantie C906
>>>> v821: Andes A27 + XuanTie E907
>>>> v861/v881: XuanTie C907
>>>>
>>>> Signed-off-by: Han Gao <gaohan at iscas.ac.cn>
>>>> ---
>>>> arch/riscv/Kconfig.socs | 22 +++++++++++++++++-----
>>>> 1 file changed, 17 insertions(+), 5 deletions(-)
>>>>
>>>> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
>>>> index 848e7149e443..7cba5d6ec4c3 100644
>>>> --- a/arch/riscv/Kconfig.socs
>>>> +++ b/arch/riscv/Kconfig.socs
>>>> @@ -54,14 +54,26 @@ config SOC_STARFIVE
>>>> 	help
>>>> 	  This enables support for StarFive SoC platform hardware.
>>>>
>>>> -config ARCH_SUNXI
>>>> -	bool "Allwinner sun20i SoCs"
>>>> +menuconfig ARCH_SUNXI
>>>> +	bool "Allwinner RISC-V SoCs"
>>>> +
>>>> +if ARCH_SUNXI
>>>> +
>>>> +config ARCH_SUNXI_XUANTIE
>>>
>>>
>>> You should not get multiple ARCHs. ARCH is only one. There is also not
>>> much rationale in commit msg for that.
>>
>> The main goal is to avoid choosing multiple IP addresses for erreta. 
>> If using Andes IPs, I don't want to choose XuanTIe (T-Head) ERRETA.
> 
> Not explained in commit msg but anyway not a good argument. It is some
> sort of micro optimization and you completely miss the point we target
> multiarch kernels.

Heh, and I actually did not forbid or discourage choosing erratas per
your soc. I said you only get one top level ARCH. Look at all arm64
platforms. How many ARCHs are there per one vendor?

Best regards,
Krzysztof