[PATCH 1/3] riscv: soc: re-organized allwinner menu

[gaohan at iscas.ac.cn]

From: Han Gao <gaohan at iscas.ac.cn>

Allwinner currently offers d1(s)/v821/v861/v881 on RISC-V,
using different IPs.

d1(s): Xuantie C906
v821: Andes A27 + XuanTie E907
v861/v881: XuanTie C907

Signed-off-by: Han Gao <gaohan at iscas.ac.cn>
---
 arch/riscv/Kconfig.socs | 22 +++++++++++++++++-----
 1 file changed, 17 insertions(+), 5 deletions(-)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 848e7149e443..7cba5d6ec4c3 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -54,14 +54,26 @@ config SOC_STARFIVE
 	help
 	  This enables support for StarFive SoC platform hardware.
 
-config ARCH_SUNXI
-	bool "Allwinner sun20i SoCs"
+menuconfig ARCH_SUNXI
+	bool "Allwinner RISC-V SoCs"
+
+if ARCH_SUNXI
+
+config ARCH_SUNXI_XUANTIE
+	bool "Allwinner Xuantie IP SoCs"
 	depends on MMU && !XIP_KERNEL
-	select ERRATA_THEAD
 	select SUN4I_TIMER
+	select ERRATA_THEAD
 	help
-	  This enables support for Allwinner sun20i platform hardware,
-	  including boards based on the D1 and D1s SoCs.
+	  This enables support for Allwinner Xuantie IP SoCs.
+
+config ARCH_SUNXI_ANDES
+	bool "Allwinner Andes IP SoCs"
+	select ERRATA_ANDES
+	help
+	  This enables support for Allwinner Andes IP SoCs.
+
+endif
 
 config ARCH_THEAD
 	bool "T-HEAD RISC-V SoCs"
-- 
2.47.3