[PATCH v1 2/3] spi: dt-binding: document Microchip CoreSPI

[Conor Dooley]

On Mon, Nov 03, 2025 at 04:05:14PM +0000, Prajna Rajendra Kumar wrote:
> Add device tree bindings for Microchip's CoreSPI controller.
> 
> CoreSPI is a "soft" IP core intended for FPGA implementations. Its
> configurations are set in Libero. These properties represent
> non-discoverable configurations determined by Verilog parameters to the
> IP.
> 
> Signed-off-by: Prajna Rajendra Kumar <prajna.rajendrakumar at microchip.com>

Reviewed-by: Conor Dooley <conor.dooley at microchip.com>
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