[PATCH v1 4/7] riscv: dts: starfive: jh7110-common: Move out some nodes to the board dts
Hal Feng
hal.feng at starfivetech.com
Sun Nov 2 21:43:19 PST 2025
> On 17.10.25 06:56, E Shattow wrote:
> On 10/16/25 01:00, Hal Feng wrote:
> > Some node in this file are not used by the upcoming VisionFive 2 Lite
> > board. Move them to the board dts to prepare for adding the new
> > VisionFive 2 Lite device tree.
> >
> > Reviewed-by: E Shattow <e at freeshell.de>
> > Signed-off-by: Hal Feng <hal.feng at starfivetech.com>
> > ---
> > .../boot/dts/starfive/jh7110-common.dtsi | 19 --------
> > .../jh7110-deepcomputing-fml13v01.dts | 46 +++++++++++++++++++
> > .../boot/dts/starfive/jh7110-milkv-mars.dts | 46 +++++++++++++++++++
> > .../dts/starfive/jh7110-milkv-marscm-emmc.dts | 9 ++++
> > .../dts/starfive/jh7110-milkv-marscm-lite.dts | 1 +
> > .../dts/starfive/jh7110-milkv-marscm.dtsi | 32 +++++++++++++
> > .../dts/starfive/jh7110-pine64-star64.dts | 46 +++++++++++++++++++
> > .../jh7110-starfive-visionfive-2.dtsi | 43 +++++++++++++++++
> > arch/riscv/boot/dts/starfive/jh7110.dtsi | 16 -------
> > 9 files changed, 223 insertions(+), 35 deletions(-)
> >
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> > b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> > index 5dc15e48b74b..8cfe8033305d 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> > +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> > @@ -281,14 +281,8 @@ &mmc0 {
> > assigned-clock-rates = <50000000>;
> > bus-width = <8>;
> > bootph-pre-ram;
> > - cap-mmc-highspeed;
> > - mmc-ddr-1_8v;
> > - mmc-hs200-1_8v;
> > - cap-mmc-hw-reset;
> > pinctrl-names = "default";
> > pinctrl-0 = <&mmc0_pins>;
> > - vmmc-supply = <&vcc_3v3>;
> > - vqmmc-supply = <&emmc_vdd>;
> > status = "okay";
> > };
> >
> > @@ -298,8 +292,6 @@ &mmc1 {
> > assigned-clock-rates = <50000000>;
> > bus-width = <4>;
> > bootph-pre-ram;
> > - cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
> > - disable-wp;
> > cap-sd-highspeed;
> > pinctrl-names = "default";
> > pinctrl-0 = <&mmc1_pins>;
> > @@ -444,17 +436,6 @@ GPOEN_SYS_I2C6_DATA,
> > };
> >
> > mmc0_pins: mmc0-0 {
> > - rst-pins {
> > - pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
> > - GPOEN_ENABLE,
> > - GPI_NONE)>;
> > - bias-pull-up;
> > - drive-strength = <12>;
> > - input-disable;
> > - input-schmitt-disable;
> > - slew-rate = <0>;
> > - };
> > -
> > mmc-pins {
> > pinmux = <PINMUX(PAD_SD0_CLK, 0)>,
> > <PINMUX(PAD_SD0_CMD, 0)>,
> > diff --git
> > a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
> > b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
> > index f2857d021d68..7535d62201f1 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
> > +++ b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
> > @@ -11,6 +11,52 @@ / {
> > compatible = "deepcomputing,fml13v01", "starfive,jh7110"; };
> >
> > +&cpu_opp {
> > + opp-375000000 {
> > + opp-hz = /bits/ 64 <375000000>;
> > + opp-microvolt = <800000>;
> > + };
> > + opp-500000000 {
> > + opp-hz = /bits/ 64 <500000000>;
> > + opp-microvolt = <800000>;
> > + };
> > + opp-750000000 {
> > + opp-hz = /bits/ 64 <750000000>;
> > + opp-microvolt = <800000>;
> > + };
> > + opp-1500000000 {
> > + opp-hz = /bits/ 64 <1500000000>;
> > + opp-microvolt = <1040000>;
> > + };
> > +};
> > +
> > +&mmc0 {
> > + cap-mmc-highspeed;
> > + cap-mmc-hw-reset;
> > + mmc-ddr-1_8v;
> > + mmc-hs200-1_8v;
> > + vmmc-supply = <&vcc_3v3>;
> > + vqmmc-supply = <&emmc_vdd>;
> > +};
> > +
> > +&mmc0_pins {
> > + rst-pins {
> > + pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
> > + GPOEN_ENABLE,
> > + GPI_NONE)>;
> > + bias-pull-up;
> > + drive-strength = <12>;
> > + input-disable;
> > + input-schmitt-disable;
> > + slew-rate = <0>;
> > + };
> > +};
> > +
> > +&mmc1 {
> > + cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
> > + disable-wp;
> > +};
> > +
> > &pcie1 {
> > perst-gpios = <&sysgpio 21 GPIO_ACTIVE_LOW>;
> > phys = <&pciephy1>;
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts
> > b/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts
> > index fdaf6b4557da..c2e7a91e460a 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts
> > +++ b/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts
> > @@ -11,6 +11,25 @@ / {
> > compatible = "milkv,mars", "starfive,jh7110"; };
> >
> > +&cpu_opp {
> > + opp-375000000 {
> > + opp-hz = /bits/ 64 <375000000>;
> > + opp-microvolt = <800000>;
> > + };
> > + opp-500000000 {
> > + opp-hz = /bits/ 64 <500000000>;
> > + opp-microvolt = <800000>;
> > + };
> > + opp-750000000 {
> > + opp-hz = /bits/ 64 <750000000>;
> > + opp-microvolt = <800000>;
> > + };
> > + opp-1500000000 {
> > + opp-hz = /bits/ 64 <1500000000>;
> > + opp-microvolt = <1040000>;
> > + };
> > +};
> > +
> > &gmac0 {
> > assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
> > assigned-clock-parents = <&aoncrg
> JH7110_AONCLK_GMAC0_RMII_RTX>; @@
> > -22,6 +41,33 @@ &i2c0 {
> > status = "okay";
> > };
> >
> > +&mmc0 {
> > + cap-mmc-highspeed;
> > + cap-mmc-hw-reset;
> > + mmc-ddr-1_8v;
> > + mmc-hs200-1_8v;
> > + vmmc-supply = <&vcc_3v3>;
> > + vqmmc-supply = <&emmc_vdd>;
> > +};
> > +
> > +&mmc0_pins {
> > + rst-pins {
> > + pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
> > + GPOEN_ENABLE,
> > + GPI_NONE)>;
> > + bias-pull-up;
> > + drive-strength = <12>;
> > + input-disable;
> > + input-schmitt-disable;
> > + slew-rate = <0>;
> > + };
> > +};
> > +
> > +&mmc1 {
> > + cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
> > + disable-wp;
> > +};
> > +
> > &pcie0 {
> > status = "okay";
> > };
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm-emmc.dts
> > b/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm-emmc.dts
> > index e568537af2c4..ce95496263af 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm-emmc.dts
> > +++ b/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm-emmc.dts
> > @@ -10,3 +10,12 @@ / {
> > model = "Milk-V Mars CM";
> > compatible = "milkv,marscm-emmc", "starfive,jh7110"; };
> > +
> > +&mmc0 {
> > + cap-mmc-highspeed;
> > + cap-mmc-hw-reset;
> > + mmc-ddr-1_8v;
> > + mmc-hs200-1_8v;
> > + vmmc-supply = <&vcc_3v3>;
> > + vqmmc-supply = <&emmc_vdd>;
> > +};
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm-lite.dts
> > b/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm-lite.dts
> > index 6c40d0ec4011..63aa94d65ab5 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm-lite.dts
> > +++ b/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm-lite.dts
> > @@ -14,6 +14,7 @@ / {
> > &mmc0 {
> > bus-width = <4>;
> > cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
> > + disable-wp;
> > };
> >
> > &mmc0_pins {
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm.dtsi
> > b/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm.dtsi
> > index 25b70af564ee..af01d3abde2f 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm.dtsi
> > +++ b/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm.dtsi
> > @@ -21,6 +21,25 @@ sdio_pwrseq: sdio-pwrseq {
> > };
> > };
> >
> > +&cpu_opp {
> > + opp-375000000 {
> > + opp-hz = /bits/ 64 <375000000>;
> > + opp-microvolt = <800000>;
> > + };
> > + opp-500000000 {
> > + opp-hz = /bits/ 64 <500000000>;
> > + opp-microvolt = <800000>;
> > + };
> > + opp-750000000 {
> > + opp-hz = /bits/ 64 <750000000>;
> > + opp-microvolt = <800000>;
> > + };
> > + opp-1500000000 {
> > + opp-hz = /bits/ 64 <1500000000>;
> > + opp-microvolt = <1040000>;
> > + };
> > +};
> > +
> > &gmac0 {
> > assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
> > assigned-clock-parents = <&aoncrg
> JH7110_AONCLK_GMAC0_RMII_RTX>; @@
> > -40,6 +59,19 @@ &i2c6 {
> > status = "disabled";
> > };
> >
> > +&mmc0_pins {
> > + rst-pins {
> > + pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
> > + GPOEN_ENABLE,
> > + GPI_NONE)>;
> > + bias-pull-up;
> > + drive-strength = <12>;
> > + input-disable;
> > + input-schmitt-disable;
> > + slew-rate = <0>;
> > + };
> > +};
> > +
> > &mmc1 {
> > #address-cells = <1>;
> > #size-cells = <0>;
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
> > b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
> > index 31e825be2065..6faf3826c5c3 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
> > +++ b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
> > @@ -14,6 +14,25 @@ aliases {
> > };
> > };
> >
> > +&cpu_opp {
> > + opp-375000000 {
> > + opp-hz = /bits/ 64 <375000000>;
> > + opp-microvolt = <800000>;
> > + };
> > + opp-500000000 {
> > + opp-hz = /bits/ 64 <500000000>;
> > + opp-microvolt = <800000>;
> > + };
> > + opp-750000000 {
> > + opp-hz = /bits/ 64 <750000000>;
> > + opp-microvolt = <800000>;
> > + };
> > + opp-1500000000 {
> > + opp-hz = /bits/ 64 <1500000000>;
> > + opp-microvolt = <1040000>;
> > + };
> > +};
> > +
> > &gmac0 {
> > starfive,tx-use-rgmii-clk;
> > assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>; @@ -
> 44,6 +63,33
> > @@ &i2c0 {
> > status = "okay";
> > };
> >
> > +&mmc0 {
> > + cap-mmc-highspeed;
> > + cap-mmc-hw-reset;
> > + mmc-ddr-1_8v;
> > + mmc-hs200-1_8v;
> > + vmmc-supply = <&vcc_3v3>;
> > + vqmmc-supply = <&emmc_vdd>;
> > +};
> > +
> > +&mmc0_pins {
> > + rst-pins {
> > + pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
> > + GPOEN_ENABLE,
> > + GPI_NONE)>;
> > + bias-pull-up;
> > + drive-strength = <12>;
> > + input-disable;
> > + input-schmitt-disable;
> > + slew-rate = <0>;
> > + };
> > +};
> > +
> > +&mmc1 {
> > + cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
> > + disable-wp;
> > +};
> > +
> > &pcie1 {
> > status = "okay";
> > };
> > diff --git
> > a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> > b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> > index 5f14afb2c24d..9cd79fe30d19 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> > @@ -13,6 +13,25 @@ aliases {
> > };
> > };
> >
> > +&cpu_opp {
> > + opp-375000000 {
> > + opp-hz = /bits/ 64 <375000000>;
> > + opp-microvolt = <800000>;
> > + };
> > + opp-500000000 {
> > + opp-hz = /bits/ 64 <500000000>;
> > + opp-microvolt = <800000>;
> > + };
> > + opp-750000000 {
> > + opp-hz = /bits/ 64 <750000000>;
> > + opp-microvolt = <800000>;
> > + };
> > + opp-1500000000 {
> > + opp-hz = /bits/ 64 <1500000000>;
> > + opp-microvolt = <1040000>;
> > + };
> > +};
> > +
> > &gmac0 {
> > status = "okay";
> > };
> > @@ -38,9 +57,33 @@ &i2c0 {
> > };
> >
> > &mmc0 {
> > + cap-mmc-highspeed;
> > + cap-mmc-hw-reset;
> > + mmc-ddr-1_8v;
> > + mmc-hs200-1_8v;
> > + vmmc-supply = <&vcc_3v3>;
> > + vqmmc-supply = <&emmc_vdd>;
> > non-removable;
> > };
> >
> > +&mmc0_pins {
> > + rst-pins {
> > + pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
> > + GPOEN_ENABLE,
> > + GPI_NONE)>;
> > + bias-pull-up;
> > + drive-strength = <12>;
> > + input-disable;
> > + input-schmitt-disable;
> > + slew-rate = <0>;
> > + };
> > +};
> > +
> > +&mmc1 {
> > + cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
> > + disable-wp;
> > +};
> > +
> > &pcie0 {
> > status = "okay";
> > };
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > index 6e56e9d20bb0..a380d3dabedd 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > @@ -205,22 +205,6 @@ core4 {
> > cpu_opp: opp-table-0 {
> > compatible = "operating-points-v2";
> > opp-shared;
> > - opp-375000000 {
> > - opp-hz = /bits/ 64 <375000000>;
> > - opp-microvolt = <800000>;
> > - };
> > - opp-500000000 {
> > - opp-hz = /bits/ 64 <500000000>;
> > - opp-microvolt = <800000>;
> > - };
> > - opp-750000000 {
> > - opp-hz = /bits/ 64 <750000000>;
> > - opp-microvolt = <800000>;
> > - };
> > - opp-1500000000 {
> > - opp-hz = /bits/ 64 <1500000000>;
> > - opp-microvolt = <1040000>;
> > - };
> > };
> >
> > thermal-zones {
>
> Emil, for your consideration:
>
> jh711x.dtsi (formerly jh7110.dtsi)
>
> jh711x-common.dtsi (formerly jh7110-common.dtsi, cut opp table and paste
> to jh7110-common.dtsi, cut out mmc definitions pasted elsewhere either to
> "mmc{0,1}-card, mmc{0,1}-emmc, mmc{0,1}-sdio" dtsi snippets or duplicated
> to board files)
>
> jh7110-common.dtsi (includes jh711x-common.dtsi, adds opp table)
>
> jh7110s-common.dtsi (includes jh711x-common.dtsi, adds opp table)
>
> This makes sense to me having two additional dtsi files of the CPU operating
> power points (on what is apparently binned silicon) to maintain for supporting
> 8+ boards. The decision to split or not split out the mmc/sdio configuration
> into common dtsi snippets is less clear to me, but we do have examples now of
> all the uses (card, eMMC, SDIO) on each of the ports mmc0 mmc1 so it might
> have some benefit; for sure keeping these assumptions about mmc0 mmc1
> functionality in the one '-common.dtsi' is an obstacle to adding sdio module
> configurations.
I agree with this suggestion. If there is no objection, I will send a new version
for review.
Best regards,
Hal
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