[PATCH v2 3/3] riscv: dts: sophgo: add zfh for sg2042

[Inochi Amaoto]

On Tue, May 27, 2025 at 06:22:05PM +0800, Chen Wang wrote:
> 
> On 2025/5/27 17:34, Han Gao wrote:
> > On Thu, May 15, 2025 at 9:33 AM Chen Wang <unicorn_wang at outlook.com> wrote:
> > > 
> > > On 2025/5/14 23:15, Han Gao wrote:
> > > > sg2042 support Zfh ISA extension [1].
> > > > 
> > > > Link: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1737721869472/%E7%8E%84%E9%93%81C910%E4%B8%8EC920R1S6%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C%28xrvm%29_20250124.pdf [1]
> > > > 
> > > > Signed-off-by: Han Gao <rabenda.cn at gmail.com>
> > > > ---
> > > >    arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 256 ++++++++++----------
> > > >    1 file changed, 128 insertions(+), 128 deletions(-)
> > > > 
> > > > diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> > > > index f483f62ab0c4..8dd1a3c60bc4 100644
> > > > --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> > > > +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> > > > @@ -256,11 +256,11 @@ core3 {
> > > >                cpu0: cpu at 0 {
> > > >                        compatible = "thead,c920", "riscv";
> > > >                        device_type = "cpu";
> > > > -                     riscv,isa = "rv64imafdc";
> > > > +                     riscv,isa = "rv64imafdc_zfh";
> > > Need not touch this. "riscv,isa" is deprecated and replaced by
> > > "riscv,isa-base" & "riscv,isa-extensions".
> > > 
> > > And only adding zfh for this looks a bit werid.
> > > 
> > > Actually, I plan to remove "riscv,isa" later, so please don't touch this
> > > from now on.
> > I think that since the linux kernel is the upstream for devicetree, it
> > cannot yet remove riscv, isa needs to maintain compatibility.
> 
> OK, maybe it's not good to remove "riscv,isa".
> 
> Can this patch not modify "riscv,isa", but only add something for
> "riscv,isa-extensions"?
> 

I can remove this while merging the patch, is it OK for you?

Regards,
Inochi