[PATCH] riscv: dts: sophgo: cv18xx: Add RTCSYS device node

[Inochi Amaoto]

On Tue, May 13, 2025 at 10:31:25PM +0200, Alexander Sverdlin wrote:
> Add the RTCSYS MFD node: in Cvitek CV18xx and its successors RTC Subsystem
> is quite advanced and provides SoC power management functions as well.
> 
> The SoC family also contains DW8051 block (Intel 8051 compatible CPU core)
> and an associated SRAM. The corresponding control registers are mapped into
> RTCSYS address space as well.
> 
> Link: https://github.com/sophgo/sophgo-doc/tree/main/SG200X/TRM
> Signed-off-by: Alexander Sverdlin <alexander.sverdlin at gmail.com>
> ---
>  arch/riscv/boot/dts/sophgo/cv180x.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 

I am happy to see the rtc driver is merged. So I will queue this
patch for the next rc1. If you need a rebase, please let me know.

Reviewed-by: Inochi Amaoto <inochiama at gmail.com>

> diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
> index ed06c3609fb2..280c45bd3b3d 100644
> --- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
> @@ -307,5 +307,17 @@ dmac: dma-controller at 4330000 {
>  			snps,data-width = <2>;
>  			status = "disabled";
>  		};
> +
> +		rtc at 5025000 {
> +			compatible = "sophgo,cv1800b-rtc", "syscon";
> +			reg = <0x5025000 0x2000>;
> +			interrupts = <SOC_PERIPHERAL_IRQ(1) IRQ_TYPE_LEVEL_HIGH>,
> +				     <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>,
> +				     <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "alarm", "longpress", "vbat";
> +			clocks = <&clk CLK_RTC_25M>,
> +				 <&clk CLK_SRC_RTC_SYS_0>;
> +			clock-names = "rtc", "mcu";
> +		};
>  	};
>  };
> -- 
> 2.49.0
>