[GIT PULL] RISC-V Sophgo Devicetrees for v6.16

[Chen Wang]

Hey Arnd,

Please pull dt changes for RISC-V/Sophgo.  Hope this PR is not too late 
for you.

In addition, I also sent a PR for sophgo/soc last week, listed here for 
your quick reference:

https://lore.kernel.org/soc/MA0P287MB2262B041A26A0F5EAD1E296CFE91A@MA0P287MB2262.INDP287.PROD.OUTLOOK.COM/


Thanks,

Chen

The following changes since commit a5806cd506af5a7c19bcd596e4708b5c464bfd21:

   Linux 6.15-rc7 (2025-05-18 13:57:29 -0700)

are available in the Git repository at:

   https://github.com/sophgo/linux.git tags/riscv-sophgo-dt-for-v6.16

for you to fetch changes up to 108a76779829a5e8001b1051080aaa93e7fc02ea:

   riscv: dts: sophgo: switch precise compatible for existed clock 
device for CV18XX (2025-05-19 06:23:26 +0800)

----------------------------------------------------------------
RISC-V Devicetrees for v6.16

Sophgo:
Add Pinctrl & SPI support for SG2042 SoC, and
refactor the dts of cv18xx to facilitate adding
support for arm core later (SG200X has two cores,
one is RISC-V and another is ARM64).
Also add initial support for Sophgo SG2044/SRD3-10.
SRD3-10 board bases on Sophgo SG2044 SoC and
initial support includes uart only. This part of
the changes involves some modifications to dts
and bindings.

Signed-off-by: Chen Wang <unicorn_wang at outlook.com>

----------------------------------------------------------------
Inochi Amaoto (10):
       riscv: dts: sophgo: sg2042: add pinctrl support
       riscv: dts: sophgo: Move all soc specific device into soc dtsi file
       riscv: dts: sophgo: Move riscv cpu definition to a separate file
       riscv: dts: sophgo: rename header file cv18xx.dtsi to cv180x.dtsi
       riscv: dts: sopgho: use SOC_PERIPHERAL_IRQ to calculate interrupt 
number
       dt-bindings: interrupt-controller: Add Sophgo SG2044 CLINT mswi
       dt-bindings: interrupt-controller: Add Sophgo SG2044 PLIC
       dt-bindings: riscv: sophgo: Add SG2044 compatible string
       riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10
       riscv: dts: sophgo: switch precise compatible for existed clock 
device for CV18XX

Zixian Zeng (1):
       riscv: sophgo: dts: Add spi controller for SG2042

  .../interrupt-controller/sifive,plic-1.0.0.yaml    |    1 +
  .../thead,c900-aclint-mswi.yaml                    |    1 +
  .../devicetree/bindings/riscv/sophgo.yaml          |    4 +
  arch/riscv/boot/dts/sophgo/Makefile                |    1 +
  arch/riscv/boot/dts/sophgo/cv1800b.dtsi            |   39 +-
  arch/riscv/boot/dts/sophgo/cv180x-cpus.dtsi        |   36 +
  .../boot/dts/sophgo/{cv18xx.dtsi => cv180x.dtsi}   |   95 +-
  arch/riscv/boot/dts/sophgo/cv1812h.dtsi            |   39 +-
  arch/riscv/boot/dts/sophgo/cv181x.dtsi             |    2 +-
  arch/riscv/boot/dts/sophgo/sg2002.dtsi             |   39 +-
  .../riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts |   72 +
  arch/riscv/boot/dts/sophgo/sg2042.dtsi             |   32 +
  arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi        | 3002 
++++++++++++++++++++
  arch/riscv/boot/dts/sophgo/sg2044-reset.h          |  128 +
  .../boot/dts/sophgo/sg2044-sophgo-srd3-10.dts      |   32 +
  arch/riscv/boot/dts/sophgo/sg2044.dtsi             |   86 +
  16 files changed, 3502 insertions(+), 107 deletions(-)
  create mode 100644 arch/riscv/boot/dts/sophgo/cv180x-cpus.dtsi
  rename arch/riscv/boot/dts/sophgo/{cv18xx.dtsi => cv180x.dtsi} (75%)
  create mode 100644 arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi
  create mode 100644 arch/riscv/boot/dts/sophgo/sg2044-reset.h
  create mode 100644 arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts
  create mode 100644 arch/riscv/boot/dts/sophgo/sg2044.dtsi