[PATCH v4 4/9] dt-bindings: interrupt-controller: add Andes machine-level software interrupt controller

[Ben Zong-You Xie]

On Wed, May 14, 2025 at 10:01:02AM -0500, Rob Herring wrote:
> [EXTERNAL MAIL]
> 
> On Wed, May 14, 2025 at 05:53:45PM +0800, Ben Zong-You Xie wrote:
> > Add the DT binding documentation for Andes machine-level software
> > interrupt controller.
> >
> > In the Andes platform such as QiLai SoC, the PLIC module is instantiated a
> > second time with all interrupt sources tied to zero as the software
> > interrupt controller (PLICSW). PLICSW can generate machine-level software
> > interrupts through programming its registers.
> >
> > Acked-by: Conor Dooley <conor.dooley at microchip.com>
> > Signed-off-by: Ben Zong-You Xie <ben717 at andestech.com>
> > ---
> >  .../andestech,plicsw.yaml                     | 54 +++++++++++++++++++
> >  MAINTAINERS                                   |  1 +
> 
> This won't apply for me due to MAINTAINERS conflict with this series. So
> apply the bindings patches with the dts files.
> 
> Rob

The conflict is due to the second patch in this series not being applied.
Should I wait for that patch to be applied, or is there something specific
I can do to resolve the conflict?

Thanks,
Ben