[PATCH v2 3/3] riscv: dts: sophgo: add zfh for sg2042
Han Gao
rabenda.cn at gmail.com
Wed May 14 08:15:52 PDT 2025
sg2042 support Zfh ISA extension [1].
Link: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1737721869472/%E7%8E%84%E9%93%81C910%E4%B8%8EC920R1S6%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C%28xrvm%29_20250124.pdf [1]
Signed-off-by: Han Gao <rabenda.cn at gmail.com>
---
arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 256 ++++++++++----------
1 file changed, 128 insertions(+), 128 deletions(-)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
index f483f62ab0c4..8dd1a3c60bc4 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
@@ -256,11 +256,11 @@ core3 {
cpu0: cpu at 0 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <0>;
@@ -283,11 +283,11 @@ cpu0_intc: interrupt-controller {
cpu1: cpu at 1 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <1>;
@@ -310,11 +310,11 @@ cpu1_intc: interrupt-controller {
cpu2: cpu at 2 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <2>;
@@ -337,11 +337,11 @@ cpu2_intc: interrupt-controller {
cpu3: cpu at 3 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <3>;
@@ -364,11 +364,11 @@ cpu3_intc: interrupt-controller {
cpu4: cpu at 4 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <4>;
@@ -391,11 +391,11 @@ cpu4_intc: interrupt-controller {
cpu5: cpu at 5 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <5>;
@@ -418,11 +418,11 @@ cpu5_intc: interrupt-controller {
cpu6: cpu at 6 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <6>;
@@ -445,11 +445,11 @@ cpu6_intc: interrupt-controller {
cpu7: cpu at 7 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <7>;
@@ -472,11 +472,11 @@ cpu7_intc: interrupt-controller {
cpu8: cpu at 8 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <8>;
@@ -499,11 +499,11 @@ cpu8_intc: interrupt-controller {
cpu9: cpu at 9 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <9>;
@@ -526,11 +526,11 @@ cpu9_intc: interrupt-controller {
cpu10: cpu at 10 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <10>;
@@ -553,11 +553,11 @@ cpu10_intc: interrupt-controller {
cpu11: cpu at 11 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <11>;
@@ -580,11 +580,11 @@ cpu11_intc: interrupt-controller {
cpu12: cpu at 12 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <12>;
@@ -607,11 +607,11 @@ cpu12_intc: interrupt-controller {
cpu13: cpu at 13 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <13>;
@@ -634,11 +634,11 @@ cpu13_intc: interrupt-controller {
cpu14: cpu at 14 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <14>;
@@ -661,11 +661,11 @@ cpu14_intc: interrupt-controller {
cpu15: cpu at 15 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <15>;
@@ -688,11 +688,11 @@ cpu15_intc: interrupt-controller {
cpu16: cpu at 16 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <16>;
@@ -715,11 +715,11 @@ cpu16_intc: interrupt-controller {
cpu17: cpu at 17 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <17>;
@@ -742,11 +742,11 @@ cpu17_intc: interrupt-controller {
cpu18: cpu at 18 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <18>;
@@ -769,11 +769,11 @@ cpu18_intc: interrupt-controller {
cpu19: cpu at 19 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <19>;
@@ -796,11 +796,11 @@ cpu19_intc: interrupt-controller {
cpu20: cpu at 20 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <20>;
@@ -823,11 +823,11 @@ cpu20_intc: interrupt-controller {
cpu21: cpu at 21 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <21>;
@@ -850,11 +850,11 @@ cpu21_intc: interrupt-controller {
cpu22: cpu at 22 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <22>;
@@ -877,11 +877,11 @@ cpu22_intc: interrupt-controller {
cpu23: cpu at 23 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <23>;
@@ -904,11 +904,11 @@ cpu23_intc: interrupt-controller {
cpu24: cpu at 24 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <24>;
@@ -931,11 +931,11 @@ cpu24_intc: interrupt-controller {
cpu25: cpu at 25 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <25>;
@@ -958,11 +958,11 @@ cpu25_intc: interrupt-controller {
cpu26: cpu at 26 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <26>;
@@ -985,11 +985,11 @@ cpu26_intc: interrupt-controller {
cpu27: cpu at 27 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <27>;
@@ -1012,11 +1012,11 @@ cpu27_intc: interrupt-controller {
cpu28: cpu at 28 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <28>;
@@ -1039,11 +1039,11 @@ cpu28_intc: interrupt-controller {
cpu29: cpu at 29 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <29>;
@@ -1066,11 +1066,11 @@ cpu29_intc: interrupt-controller {
cpu30: cpu at 30 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <30>;
@@ -1093,11 +1093,11 @@ cpu30_intc: interrupt-controller {
cpu31: cpu at 31 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <31>;
@@ -1120,11 +1120,11 @@ cpu31_intc: interrupt-controller {
cpu32: cpu at 32 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <32>;
@@ -1147,11 +1147,11 @@ cpu32_intc: interrupt-controller {
cpu33: cpu at 33 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <33>;
@@ -1174,11 +1174,11 @@ cpu33_intc: interrupt-controller {
cpu34: cpu at 34 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <34>;
@@ -1201,11 +1201,11 @@ cpu34_intc: interrupt-controller {
cpu35: cpu at 35 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <35>;
@@ -1228,11 +1228,11 @@ cpu35_intc: interrupt-controller {
cpu36: cpu at 36 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <36>;
@@ -1255,11 +1255,11 @@ cpu36_intc: interrupt-controller {
cpu37: cpu at 37 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <37>;
@@ -1282,11 +1282,11 @@ cpu37_intc: interrupt-controller {
cpu38: cpu at 38 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <38>;
@@ -1309,11 +1309,11 @@ cpu38_intc: interrupt-controller {
cpu39: cpu at 39 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <39>;
@@ -1336,11 +1336,11 @@ cpu39_intc: interrupt-controller {
cpu40: cpu at 40 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <40>;
@@ -1363,11 +1363,11 @@ cpu40_intc: interrupt-controller {
cpu41: cpu at 41 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <41>;
@@ -1390,11 +1390,11 @@ cpu41_intc: interrupt-controller {
cpu42: cpu at 42 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <42>;
@@ -1417,11 +1417,11 @@ cpu42_intc: interrupt-controller {
cpu43: cpu at 43 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <43>;
@@ -1444,11 +1444,11 @@ cpu43_intc: interrupt-controller {
cpu44: cpu at 44 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <44>;
@@ -1471,11 +1471,11 @@ cpu44_intc: interrupt-controller {
cpu45: cpu at 45 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <45>;
@@ -1498,11 +1498,11 @@ cpu45_intc: interrupt-controller {
cpu46: cpu at 46 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <46>;
@@ -1525,11 +1525,11 @@ cpu46_intc: interrupt-controller {
cpu47: cpu at 47 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <47>;
@@ -1552,11 +1552,11 @@ cpu47_intc: interrupt-controller {
cpu48: cpu at 48 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <48>;
@@ -1579,11 +1579,11 @@ cpu48_intc: interrupt-controller {
cpu49: cpu at 49 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <49>;
@@ -1606,11 +1606,11 @@ cpu49_intc: interrupt-controller {
cpu50: cpu at 50 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <50>;
@@ -1633,11 +1633,11 @@ cpu50_intc: interrupt-controller {
cpu51: cpu at 51 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <51>;
@@ -1660,11 +1660,11 @@ cpu51_intc: interrupt-controller {
cpu52: cpu at 52 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <52>;
@@ -1687,11 +1687,11 @@ cpu52_intc: interrupt-controller {
cpu53: cpu at 53 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <53>;
@@ -1714,11 +1714,11 @@ cpu53_intc: interrupt-controller {
cpu54: cpu at 54 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <54>;
@@ -1741,11 +1741,11 @@ cpu54_intc: interrupt-controller {
cpu55: cpu at 55 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <55>;
@@ -1768,11 +1768,11 @@ cpu55_intc: interrupt-controller {
cpu56: cpu at 56 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <56>;
@@ -1795,11 +1795,11 @@ cpu56_intc: interrupt-controller {
cpu57: cpu at 57 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <57>;
@@ -1822,11 +1822,11 @@ cpu57_intc: interrupt-controller {
cpu58: cpu at 58 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <58>;
@@ -1849,11 +1849,11 @@ cpu58_intc: interrupt-controller {
cpu59: cpu at 59 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <59>;
@@ -1876,11 +1876,11 @@ cpu59_intc: interrupt-controller {
cpu60: cpu at 60 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <60>;
@@ -1903,11 +1903,11 @@ cpu60_intc: interrupt-controller {
cpu61: cpu at 61 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <61>;
@@ -1930,11 +1930,11 @@ cpu61_intc: interrupt-controller {
cpu62: cpu at 62 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <62>;
@@ -1957,11 +1957,11 @@ cpu62_intc: interrupt-controller {
cpu63: cpu at 63 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <63>;
--
2.47.2
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