[PATCH 1/2] riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree
Chen Wang
unicorn_wang at outlook.com
Tue May 13 01:06:15 PDT 2025
On 2025/5/13 14:45, Han Gao wrote:
> You can use xxd to convert it.
>
> cat /sys/devices/system/cpu/cpu63/of_node/thead,vlenb | xxd
> 00000000: 0000 0080 ....
>
> Regards,
> Han
I can read this after disable ERRATA_THEAD_GHOSTWRITE.
I recommend adding some explanation notes in the commit message. For
example, when we need to enable xtheadvector, the prerequisite is to
turn off "ERRATA_THEAD_GHOSTWRITE".
I found the relevant patch is
https://lore.kernel.org/linux-riscv/20241113-xtheadvector-v11-0-236c22791ef9@rivosinc.com/,
also hope adding this will help later people quickly understand and
avoid my mistakes.
One more question is about writing value of "thead,vlenb". See bindings
description in Documentation/devicetree/bindings/riscv/cpus.yaml:
```
thead,vlenb:
$ref: /schemas/types.yaml#/definitions/uint32
description:
VLEN/8, the vector register length in bytes. This property is
required on
thead systems where the vector register length is not identical
on all harts, or
the vlenb CSR is not available.
```
What I am not sure about is whether we should write 128 or 128/8=16?
Assuming VLEN of C910 is 128bit.
Thanks,
Chen
>
> On Tue, May 13, 2025 at 9:19 AM Chen Wang <unicorn_wang at outlook.com> wrote:
>> Hi，Han,
>>
>> I tested with this patch and the machine can bootup. But I find when I
>> run "cat /sys/devices/system/cpu/cpu63/of_node/thead,vlenb", it print
>> nothing, though I expect to see 128.
>>
>> Do you know why?
>>
>> Regards,
>>
>> Chen
>>
>> On 2025/5/10 6:11, Han Gao wrote:
>>> The sg2042 SoCs support xtheadvector so it can be included in the
>>> devicetree. Also include vlenb for the cpu.
>>>
>>> Signed-off-by: Han Gao <rabenda.cn at gmail.com>
>>> ---
>>> arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 192 +++++++++++++-------
>>> 1 file changed, 128 insertions(+), 64 deletions(-)
>>>
>>> diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
>>> index b136b6c4128c..927e0260acbd 100644
>>> --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
>>> +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
>>> @@ -260,7 +260,8 @@ cpu0: cpu at 0 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <0>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -285,7 +286,8 @@ cpu1: cpu at 1 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <1>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -310,7 +312,8 @@ cpu2: cpu at 2 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <2>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -335,7 +338,8 @@ cpu3: cpu at 3 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <3>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -360,7 +364,8 @@ cpu4: cpu at 4 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <4>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -385,7 +390,8 @@ cpu5: cpu at 5 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <5>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -410,7 +416,8 @@ cpu6: cpu at 6 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <6>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -435,7 +442,8 @@ cpu7: cpu at 7 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <7>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -460,7 +468,8 @@ cpu8: cpu at 8 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <8>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -485,7 +494,8 @@ cpu9: cpu at 9 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <9>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -510,7 +520,8 @@ cpu10: cpu at 10 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <10>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -535,7 +546,8 @@ cpu11: cpu at 11 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <11>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -560,7 +572,8 @@ cpu12: cpu at 12 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <12>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -585,7 +598,8 @@ cpu13: cpu at 13 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <13>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -610,7 +624,8 @@ cpu14: cpu at 14 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <14>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -635,7 +650,8 @@ cpu15: cpu at 15 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <15>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -660,7 +676,8 @@ cpu16: cpu at 16 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <16>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -685,7 +702,8 @@ cpu17: cpu at 17 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <17>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -710,7 +728,8 @@ cpu18: cpu at 18 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <18>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -735,7 +754,8 @@ cpu19: cpu at 19 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <19>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -760,7 +780,8 @@ cpu20: cpu at 20 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <20>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -785,7 +806,8 @@ cpu21: cpu at 21 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <21>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -810,7 +832,8 @@ cpu22: cpu at 22 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <22>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -835,7 +858,8 @@ cpu23: cpu at 23 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <23>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -860,7 +884,8 @@ cpu24: cpu at 24 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <24>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -885,7 +910,8 @@ cpu25: cpu at 25 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <25>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -910,7 +936,8 @@ cpu26: cpu at 26 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <26>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -935,7 +962,8 @@ cpu27: cpu at 27 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <27>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -960,7 +988,8 @@ cpu28: cpu at 28 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <28>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -985,7 +1014,8 @@ cpu29: cpu at 29 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <29>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -1010,7 +1040,8 @@ cpu30: cpu at 30 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <30>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -1035,7 +1066,8 @@ cpu31: cpu at 31 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <31>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -1060,7 +1092,8 @@ cpu32: cpu at 32 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <32>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -1085,7 +1118,8 @@ cpu33: cpu at 33 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <33>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -1110,7 +1144,8 @@ cpu34: cpu at 34 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <34>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -1135,7 +1170,8 @@ cpu35: cpu at 35 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <35>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -1160,7 +1196,8 @@ cpu36: cpu at 36 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <36>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -1185,7 +1222,8 @@ cpu37: cpu at 37 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <37>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -1210,7 +1248,8 @@ cpu38: cpu at 38 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <38>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -1235,7 +1274,8 @@ cpu39: cpu at 39 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <39>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -1260,7 +1300,8 @@ cpu40: cpu at 40 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <40>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -1285,7 +1326,8 @@ cpu41: cpu at 41 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <41>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -1310,7 +1352,8 @@ cpu42: cpu at 42 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <42>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -1335,7 +1378,8 @@ cpu43: cpu at 43 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <43>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -1360,7 +1404,8 @@ cpu44: cpu at 44 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <44>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -1385,7 +1430,8 @@ cpu45: cpu at 45 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <45>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -1410,7 +1456,8 @@ cpu46: cpu at 46 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <46>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -1435,7 +1482,8 @@ cpu47: cpu at 47 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <47>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -1460,7 +1508,8 @@ cpu48: cpu at 48 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <48>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -1485,7 +1534,8 @@ cpu49: cpu at 49 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <49>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -1510,7 +1560,8 @@ cpu50: cpu at 50 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <50>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -1535,7 +1586,8 @@ cpu51: cpu at 51 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <51>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -1560,7 +1612,8 @@ cpu52: cpu at 52 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <52>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -1585,7 +1638,8 @@ cpu53: cpu at 53 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <53>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -1610,7 +1664,8 @@ cpu54: cpu at 54 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <54>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -1635,7 +1690,8 @@ cpu55: cpu at 55 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <55>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -1660,7 +1716,8 @@ cpu56: cpu at 56 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <56>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -1685,7 +1742,8 @@ cpu57: cpu at 57 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <57>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -1710,7 +1768,8 @@ cpu58: cpu at 58 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <58>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -1735,7 +1794,8 @@ cpu59: cpu at 59 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <59>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -1760,7 +1820,8 @@ cpu60: cpu at 60 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <60>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -1785,7 +1846,8 @@ cpu61: cpu at 61 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <61>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -1810,7 +1872,8 @@ cpu62: cpu at 62 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <62>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
>>> @@ -1835,7 +1898,8 @@ cpu63: cpu at 63 {
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "zicntr", "zicsr", "zifencei",
>>> - "zihpm";
>>> + "zihpm", "xtheadvector";
>>> + thead,vlenb = <128>;
>>> reg = <63>;
>>> i-cache-block-size = <64>;
>>> i-cache-size = <65536>;
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