[PATCH v2 2/2] riscv: dts: renesas: add specific RZ/Five cache compatible

[Geert Uytterhoeven]

Hi Conor,

On Mon, 12 May 2025 at 15:48, Conor Dooley <conor at kernel.org> wrote:
> From: Conor Dooley <conor.dooley at microchip.com>
>
> When the binding was originally written, it was assumed that all
> ax45mp-caches had the same properties etc. This has turned out to be
> incorrect, as the QiLai SoC has a different number of cache-sets.
>
> Add a specific compatible for the RZ/Five for property enforcement and
> in case there turns out to be additional differences between these
> implementations of the cache controller.
>
> Acked-by: Ben Zong-You Xie <ben717 at andestech.com>
> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>

Thanks for the update!

> --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> @@ -143,7 +143,8 @@ plic: interrupt-controller at 12c00000 {
>         };
>
>         l2cache: cache-controller at 13400000 {
> -               compatible = "andestech,ax45mp-cache", "cache";
> +               compatible = "renesas,r9a07g043f-ax45mp-cache", "andestech,ax45mp-cache",
> +                            "cache";
>                 reg = <0x0 0x13400000 0x0 0x100000>;
>                 interrupts = <SOC_PERIPHERAL_IRQ(476) IRQ_TYPE_LEVEL_HIGH>;
>                 cache-size = <0x40000>;

Reviewed-by: Geert Uytterhoeven <geert+renesas at glider.be>
i.e. will queue in renesas-devel for v6.16 if there are no objections.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

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when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds