[PATCH 2/2] riscv: dts: sophgo: add ziccrse for sg2042
Han Gao
rabenda.cn at gmail.com
Fri May 9 15:11:23 PDT 2025
sg2042 support Ziccrse ISA extension [1].
Link: https://lore.kernel.org/all/20241103145153.105097-12-alexghiti@rivosinc.com/ [1]
Signed-off-by: Han Gao <rabenda.cn at gmail.com>
---
arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 128 ++++++++++----------
1 file changed, 64 insertions(+), 64 deletions(-)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
index 927e0260acbd..04a6875574bb 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
@@ -259,7 +259,7 @@ cpu0: cpu at 0 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <0>;
@@ -285,7 +285,7 @@ cpu1: cpu at 1 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <1>;
@@ -311,7 +311,7 @@ cpu2: cpu at 2 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <2>;
@@ -337,7 +337,7 @@ cpu3: cpu at 3 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <3>;
@@ -363,7 +363,7 @@ cpu4: cpu at 4 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <4>;
@@ -389,7 +389,7 @@ cpu5: cpu at 5 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <5>;
@@ -415,7 +415,7 @@ cpu6: cpu at 6 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <6>;
@@ -441,7 +441,7 @@ cpu7: cpu at 7 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <7>;
@@ -467,7 +467,7 @@ cpu8: cpu at 8 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <8>;
@@ -493,7 +493,7 @@ cpu9: cpu at 9 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <9>;
@@ -519,7 +519,7 @@ cpu10: cpu at 10 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <10>;
@@ -545,7 +545,7 @@ cpu11: cpu at 11 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <11>;
@@ -571,7 +571,7 @@ cpu12: cpu at 12 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <12>;
@@ -597,7 +597,7 @@ cpu13: cpu at 13 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <13>;
@@ -623,7 +623,7 @@ cpu14: cpu at 14 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <14>;
@@ -649,7 +649,7 @@ cpu15: cpu at 15 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <15>;
@@ -675,7 +675,7 @@ cpu16: cpu at 16 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <16>;
@@ -701,7 +701,7 @@ cpu17: cpu at 17 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <17>;
@@ -727,7 +727,7 @@ cpu18: cpu at 18 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <18>;
@@ -753,7 +753,7 @@ cpu19: cpu at 19 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <19>;
@@ -779,7 +779,7 @@ cpu20: cpu at 20 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <20>;
@@ -805,7 +805,7 @@ cpu21: cpu at 21 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <21>;
@@ -831,7 +831,7 @@ cpu22: cpu at 22 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <22>;
@@ -857,7 +857,7 @@ cpu23: cpu at 23 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <23>;
@@ -883,7 +883,7 @@ cpu24: cpu at 24 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <24>;
@@ -909,7 +909,7 @@ cpu25: cpu at 25 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <25>;
@@ -935,7 +935,7 @@ cpu26: cpu at 26 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <26>;
@@ -961,7 +961,7 @@ cpu27: cpu at 27 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <27>;
@@ -987,7 +987,7 @@ cpu28: cpu at 28 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <28>;
@@ -1013,7 +1013,7 @@ cpu29: cpu at 29 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <29>;
@@ -1039,7 +1039,7 @@ cpu30: cpu at 30 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <30>;
@@ -1065,7 +1065,7 @@ cpu31: cpu at 31 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <31>;
@@ -1091,7 +1091,7 @@ cpu32: cpu at 32 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <32>;
@@ -1117,7 +1117,7 @@ cpu33: cpu at 33 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <33>;
@@ -1143,7 +1143,7 @@ cpu34: cpu at 34 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <34>;
@@ -1169,7 +1169,7 @@ cpu35: cpu at 35 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <35>;
@@ -1195,7 +1195,7 @@ cpu36: cpu at 36 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <36>;
@@ -1221,7 +1221,7 @@ cpu37: cpu at 37 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <37>;
@@ -1247,7 +1247,7 @@ cpu38: cpu at 38 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <38>;
@@ -1273,7 +1273,7 @@ cpu39: cpu at 39 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <39>;
@@ -1299,7 +1299,7 @@ cpu40: cpu at 40 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <40>;
@@ -1325,7 +1325,7 @@ cpu41: cpu at 41 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <41>;
@@ -1351,7 +1351,7 @@ cpu42: cpu at 42 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <42>;
@@ -1377,7 +1377,7 @@ cpu43: cpu at 43 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <43>;
@@ -1403,7 +1403,7 @@ cpu44: cpu at 44 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <44>;
@@ -1429,7 +1429,7 @@ cpu45: cpu at 45 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <45>;
@@ -1455,7 +1455,7 @@ cpu46: cpu at 46 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <46>;
@@ -1481,7 +1481,7 @@ cpu47: cpu at 47 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <47>;
@@ -1507,7 +1507,7 @@ cpu48: cpu at 48 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <48>;
@@ -1533,7 +1533,7 @@ cpu49: cpu at 49 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <49>;
@@ -1559,7 +1559,7 @@ cpu50: cpu at 50 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <50>;
@@ -1585,7 +1585,7 @@ cpu51: cpu at 51 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <51>;
@@ -1611,7 +1611,7 @@ cpu52: cpu at 52 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <52>;
@@ -1637,7 +1637,7 @@ cpu53: cpu at 53 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <53>;
@@ -1663,7 +1663,7 @@ cpu54: cpu at 54 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <54>;
@@ -1689,7 +1689,7 @@ cpu55: cpu at 55 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <55>;
@@ -1715,7 +1715,7 @@ cpu56: cpu at 56 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <56>;
@@ -1741,7 +1741,7 @@ cpu57: cpu at 57 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <57>;
@@ -1767,7 +1767,7 @@ cpu58: cpu at 58 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <58>;
@@ -1793,7 +1793,7 @@ cpu59: cpu at 59 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <59>;
@@ -1819,7 +1819,7 @@ cpu60: cpu at 60 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <60>;
@@ -1845,7 +1845,7 @@ cpu61: cpu at 61 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <61>;
@@ -1871,7 +1871,7 @@ cpu62: cpu at 62 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <62>;
@@ -1897,7 +1897,7 @@ cpu63: cpu at 63 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "zicntr", "zicsr", "zifencei",
+ "ziccrse", "zicntr", "zicsr", "zifencei",
"zihpm", "xtheadvector";
thead,vlenb = <128>;
reg = <63>;
--
2.47.2
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