[PATCH v2 5/9] dt-bindings: timer: add Andes machine timer

[Conor Dooley]

On Sat, May 03, 2025 at 11:18:25PM +0800, Ben Zong-You Xie wrote:
> Add the DT binding documentation for Andes machine timer.
> 
> The RISC-V architecture defines a machine timer that provides a real-time
> counter and generates timer interrupts. Andes machiner timer (PLMT0) is
> the implementation of the machine timer, and it contains memory-mapped
> registers (mtime and mtimecmp). This device supports up to 32 cores.
> 
> Signed-off-by: Ben Zong-You Xie <ben717 at andestech.com>

Acked-by: Conor Dooley <conor.dooley at microchip.com>
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