On Tue, Feb 4, 2025 at 4:28 AM Rob Herring <robh at kernel.org> wrote:
>
> On Mon, Feb 03, 2025 at 02:18:59PM +0530, Anup Patel wrote:
> > Add device tree bindings for the system MSI service group based interrupt
> > controller defined by the RISC-V platform management interface (RPMI)
> > specification.
> >
> > Signed-off-by: Anup Patel <apatel at ventanamicro.com>
> > ---
> > .../riscv,rpmi-system-msi.yaml | 89 +++++++++++++++++++
> > 1 file changed, 89 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,rpmi-system-msi.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,rpmi-system-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,rpmi-system-msi.yaml
> > new file mode 100644
> > index 000000000000..e6c297e66c99
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,rpmi-system-msi.yaml
> > @@ -0,0 +1,89 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/interrupt-controller/riscv,rpmi-system-msi.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: RISC-V RPMI system MSI service group based interrupt controller
> > +
> > +maintainers:
> > + - Anup Patel <anup at brainfault.org>
> > +
> > +description: |
> > + The RISC-V Platform Management Interface (RPMI) [1] defines a
> > + messaging protocol which is modular and extensible. The supervisor
> > + software can send/receive RPMI messages via SBI MPXY extension [2]
> > + or some dedicated supervisor-mode RPMI transport.
> > +
> > + The RPMI specification [1] defines system MSI service group which
> > + allow application processors to receive MSIs upon system events
> > + such as P2A doorbell, graceful shutdown/reboot request, CPU hotplug
> > + event, memory hotplug event, etc from the platform microcontroller.
>
> I'm confused by this description and what the binding has. This "device"
> is receiving interrupts and generating MSIs based on those interrupts?
The platform microcontroller receives/monitors system events and
sends MSI to application processors (RISC-V CPUs).
>
> > +
> > + ===========================================
> > + References
> > + ===========================================
> > +
> > + [1] RISC-V Platform Management Interface (RPMI)
> > + https://github.com/riscv-non-isa/riscv-rpmi/releases
> > +
> > + [2] RISC-V Supervisor Binary Interface (SBI)
> > + https://github.com/riscv-non-isa/riscv-sbi-doc/releases
> > +
> > +allOf:
> > + - $ref: /schemas/interrupt-controller.yaml#
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - description:
> > + Intended for use by the SBI implementation in machine mode or
> > + software in supervisor mode.
> > + const: riscv,rpmi-system-msi
> > +
> > + - description:
> > + Intended for use by the SBI implementation in machine mode.
> > + const: riscv,rpmi-mpxy-system-msi
> > +
> > + mboxes:
> > + maxItems: 1
> > + description:
> > + Mailbox channel of the underlying RPMI transport or SBI message proxy.
> > +
> > + riscv,sbi-mpxy-channel-id:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + description:
> > + The SBI MPXY channel id to be used for providing RPMI access to
> > + the supervisor software. This property is mandatory when using
> > + riscv,rpmi-mpxy-system-msi compatible string.
> > +
> > + msi-parent: true
> > +
> > + interrupt-controller: true
> > +
> > + "#interrupt-cells":
> > + const: 1
> > +
> > +required:
> > + - compatible
> > + - mboxes
> > + - msi-parent
> > + - interrupt-controller
> > + - "#interrupt-cells"
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + mpxy_mbox: sbi-mpxy-mbox {
>
> mailbox {
>
> Though generally we don't show providers for a consumer schema.
Okay, I will drop the producer schema.
>
> > + compatible = "riscv,sbi-mpxy-mbox";
> > + #mbox-cells = <2>;
> > + };
> > + rpmi_sysmsi_intc: interrupt-controller {
> > + compatible = "riscv,rpmi-system-msi";
> > + mboxes = <&mpxy_mbox 0x2000 0x0>;
> > + msi-parent = <&imsic_slevel>;
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > +...
> > --
> > 2.43.0
> >
Regards,
Anup