[PATCH v3 6/7] riscv: add a data fence for CMODX in the kernel mode

[Andy Chiu]

Andrea Parri <parri.andrea at gmail.com> 於 2025年3月12日 週三 上午2:11寫道：
>
> On Tue, Mar 11, 2025 at 03:53:36PM +0100, Björn Töpel wrote:
> > Andrea Parri <parri.andrea at gmail.com> writes:
> >
> > >> FWIW, the for S-IMSIC the write is already writel(), so we'll have the
> > >> text patching and IPI ordered. Regardless, there's more than one flavor
> > >> of IPI on RISC-V!
> > >
> > > AFAIU, this writel() is intended to order the insertion (and the initialization)
> > > of the CSD object before the MMIO writes; so, the "right fix" seems to turn the
> > > "other flavors" into using a writel() or providing a similar ordering guarantee.

I found that Apple's aic irqchip uses writel_relaxed for sending IPIs.
I am not sure if it is a practice using relaxed mmio in the driver to
deal with IPIs. I am more convinced that driver should use the relaxed
version if there is no data/io dependency for the driver itself. But
it is true that a fence in the driver makes programming easier.

> >
> > Yes, that's probably the right approach, or maybe follow-up!
> >
> > > As a bonus, such change should address/fix all current and future occurrences of
> > > the message-passing scenario in question (the patch addressed the occurrence in
> > > flush_icache_all(), but there appears to be a similar one in flush_icache_mm()).
> >
> > Indeed. I wonder if the SBI remote fence.i needs it?
>
> Ah!  So I am not alone: AFAICT, that remains a matter of discussions with your SEE
> team/developers.  :-|

As far as OpenSBI is concerned, there is a wmb(), which translated to
fence ow, ow, in the generic code path. Regardless, there may be more
than one flavor of SBIs, should we also consider that?

Thanks,
Andy