[PATCH v3 3/4] spi: spi-sg2044-nor: Fix reading bytes issue on SG2042

[Zixian Zeng]

SG2042 spi flash controller specification[1] states that:
> For Receive, an interrupt and DMA request are generated
> when the number of valid bytes in the FIFO is greater than
> or equal to the number of bytes defined by FFTrgLvl.

Auto-detecting flash with SFDP only requires reading 4 bytes
in spi_nor_check_sfdp_signature().
Because of that, no interrupt is triggered and a timeout happens instead.
Since we want to reuse this driver for SG2042, setting FFTrgLvl to a value
which is less than or equal to 4 should solve the issue.

Link: https://github.com/sophgo/sophgo-doc/blob/main/SG2042/TRM/source/SPI-flash.rst [1]
Signed-off-by: Zixian Zeng <sycamoremoon376 at gmail.com>
---
 drivers/spi/spi-sg2044-nor.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/spi/spi-sg2044-nor.c b/drivers/spi/spi-sg2044-nor.c
index 09a5712822e32c9da818684e7010b70aa94ae347..c1fe43e09c549328c0d046fc95bed130083dbbcb 100644
--- a/drivers/spi/spi-sg2044-nor.c
+++ b/drivers/spi/spi-sg2044-nor.c
@@ -485,8 +485,14 @@ static const struct sg2044_spifmc_chip_info sg2044_chip_info = {
 	.rd_fifo_int_trigger_level = SPIFMC_TRAN_CSR_FIFO_TRG_LVL_8_BYTE,
 };
 
+static const struct sg2044_spifmc_chip_info sg2042_chip_info = {
+	.has_opt_reg = false,
+	.rd_fifo_int_trigger_level = SPIFMC_TRAN_CSR_FIFO_TRG_LVL_1_BYTE,
+};
+
 static const struct of_device_id sg2044_spifmc_match[] = {
 	{ .compatible = "sophgo,sg2044-spifmc-nor", .data = &sg2044_chip_info },
+	{ .compatible = "sophgo,sg2042-spifmc-nor", .data = &sg2042_chip_info },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, sg2044_spifmc_match);

-- 
2.49.0