[PATCH v3 3/7] dt-bindings: interrupt-controller: add MIPS P8700 aclint-sswi

[Conor Dooley]

On Thu, Jun 12, 2025 at 05:39:07PM +0300, Vladimir Kondratiev wrote:
> Add ACLINT-SSWI variant for the MIPS P8700. This CPU has
> SSWI device compliant with the RISC-V draft spec (see [1])
> CPU indexes on this platform are not contiguous, instead
> it uses bit-fields to encode hart,core,cluster numbers, thus
> property "riscv,hart-indexes" is mandatory
> 
> Link: https://github.com/riscvarchive/riscv-aclint [1]
> 
^ this blank line shouldn't be here fwiw.

> Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev at mobileye.com>

Acked-by: Conor Dooley <conor.dooley at microchip.com>
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