[PATCH v3 2/3] riscv: Optimize gcd() code size when CONFIG_RISCV_ISA_ZBB is disabled
Alexandre Ghiti
alex at ghiti.fr
Thu Jun 12 05:59:24 PDT 2025
Hi Kuan-Wei,
On 6/6/25 15:47, Kuan-Wei Chiu wrote:
> The binary GCD implementation depends on efficient ffs(), which on
> RISC-V requires hardware support for the Zbb extension. When
> CONFIG_RISCV_ISA_ZBB is not enabled, the kernel will never use binary
> GCD, as runtime logic will always fall back to the odd-even
> implementation.
>
> To avoid compiling unused code and reduce code size, select
> CONFIG_CPU_NO_EFFICIENT_FFS when CONFIG_RISCV_ISA_ZBB is not set.
>
> $ ./scripts/bloat-o-meter ./lib/math/gcd.o.old ./lib/math/gcd.o.new
> add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-274 (-274)
> Function old new delta
> gcd 360 86 -274
> Total: Before=384, After=110, chg -71.35%
>
> Co-developed-by: Yu-Chun Lin <eleanor15x at gmail.com>
> Signed-off-by: Yu-Chun Lin <eleanor15x at gmail.com>
> Signed-off-by: Kuan-Wei Chiu <visitorckw at gmail.com>
> ---
> arch/riscv/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index bbec87b79309..f085adc6f573 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -95,6 +95,7 @@ config RISCV
> select CLINT_TIMER if RISCV_M_MODE
> select CLONE_BACKWARDS
> select COMMON_CLK
> + select CPU_NO_EFFICIENT_FFS if !RISCV_ISA_ZBB
> select CPU_PM if CPU_IDLE || HIBERNATION || SUSPEND
> select EDAC_SUPPORT
> select FRAME_POINTER if PERF_EVENTS || (FUNCTION_TRACER && !DYNAMIC_FTRACE)
In v2, Andrew asked if he could merge it, so:
Acked-by: Alexandre Ghiti <alexghiti at rivosinc.com>
Thanks,
Alex
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