[PATCH v3 4/4] riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC
Inochi Amaoto
inochiama at gmail.com
Wed Jun 11 00:53:18 PDT 2025
Add known reset configuration for existed device.
Signed-off-by: Inochi Amaoto <inochiama at gmail.com>
Reviewed-by: Alexander Sverdlin <alexander.sverdlin at gmail.com>
---
arch/riscv/boot/dts/sophgo/cv180x.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
index 4c3d16764131..e91bb512b099 100644
--- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
@@ -36,6 +36,7 @@ gpio0: gpio at 3020000 {
reg = <0x3020000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
+ resets = <&rst RST_GPIO0>;
porta: gpio-controller at 0 {
compatible = "snps,dw-apb-gpio-port";
@@ -54,6 +55,7 @@ gpio1: gpio at 3021000 {
reg = <0x3021000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
+ resets = <&rst RST_GPIO1>;
portb: gpio-controller at 0 {
compatible = "snps,dw-apb-gpio-port";
@@ -72,6 +74,7 @@ gpio2: gpio at 3022000 {
reg = <0x3022000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
+ resets = <&rst RST_GPIO2>;
portc: gpio-controller at 0 {
compatible = "snps,dw-apb-gpio-port";
@@ -90,6 +93,7 @@ gpio3: gpio at 3023000 {
reg = <0x3023000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
+ resets = <&rst RST_GPIO3>;
portd: gpio-controller at 0 {
compatible = "snps,dw-apb-gpio-port";
@@ -133,6 +137,7 @@ i2c0: i2c at 4000000 {
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>;
clock-names = "ref", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_I2C0>;
status = "disabled";
};
@@ -144,6 +149,7 @@ i2c1: i2c at 4010000 {
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>;
clock-names = "ref", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_I2C1>;
status = "disabled";
};
@@ -155,6 +161,7 @@ i2c2: i2c at 4020000 {
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>;
clock-names = "ref", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_I2C2>;
status = "disabled";
};
@@ -166,6 +173,7 @@ i2c3: i2c at 4030000 {
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>;
clock-names = "ref", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_I2C3>;
status = "disabled";
};
@@ -177,6 +185,7 @@ i2c4: i2c at 4040000 {
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>;
clock-names = "ref", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_I2C4>;
status = "disabled";
};
@@ -188,6 +197,7 @@ uart0: serial at 4140000 {
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
+ resets = <&rst RST_UART0>;
status = "disabled";
};
@@ -199,6 +209,7 @@ uart1: serial at 4150000 {
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
+ resets = <&rst RST_UART1>;
status = "disabled";
};
@@ -210,6 +221,7 @@ uart2: serial at 4160000 {
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
+ resets = <&rst RST_UART2>;
status = "disabled";
};
@@ -221,6 +233,7 @@ uart3: serial at 4170000 {
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
+ resets = <&rst RST_UART3>;
status = "disabled";
};
@@ -232,6 +245,7 @@ spi0: spi at 4180000 {
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>;
clock-names = "ssi_clk", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_SPI0>;
status = "disabled";
};
@@ -243,6 +257,7 @@ spi1: spi at 4190000 {
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>;
clock-names = "ssi_clk", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_SPI1>;
status = "disabled";
};
@@ -254,6 +269,7 @@ spi2: spi at 41a0000 {
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>;
clock-names = "ssi_clk", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_SPI2>;
status = "disabled";
};
@@ -265,6 +281,7 @@ spi3: spi at 41b0000 {
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>;
clock-names = "ssi_clk", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_SPI3>;
status = "disabled";
};
@@ -276,6 +293,7 @@ uart4: serial at 41c0000 {
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
+ resets = <&rst RST_UART4>;
status = "disabled";
};
--
2.49.0
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