[GIT PULL] RISC-V Patches for the 6.16 Merge Window, Part 3

[Alexandre Ghiti]

The following changes since commit dc5240f09bca7b5fc72ad8894d6b9321bce51139:

   RISC-V: vDSO: Wire up getrandom() vDSO implementation (2025-05-23 
12:53:18 +0000)

are available in the Git repository at:

   git://git.kernel.org/pub/scm/linux/kernel/git/alexghiti/linux 
tags/riscv-mw3-6.16-rc1

for you to fetch changes up to 0036298021eae09ec93167a5e4721bfe122d828b:

   Merge patch series "riscv: misaligned: fix misaligned accesses 
handling in put/get_user()" (2025-06-04 11:59:51 +0000)

----------------------------------------------------------------
riscv patches for 6.16-rc1, part 3

* Add SBI FWFT support

----------------------------------------------------------------
Alexandre Ghiti (3):
       Merge patch series "riscv: add SBI FWFT misaligned exception 
delegation support"
       riscv: make unsafe user copy routines use existing assembly routines
       Merge patch series "riscv: misaligned: fix misaligned accesses 
handling in put/get_user()"

Clément Léger (13):
       riscv: sbi: add Firmware Feature (FWFT) SBI extensions definitions
       riscv: sbi: remove useless parenthesis
       riscv: sbi: add new SBI error mappings
       riscv: sbi: add FWFT extension interface
       riscv: sbi: add SBI FWFT extension calls
       riscv: misaligned: request misaligned exception from SBI
       riscv: misaligned: use on_each_cpu() for scalar misaligned access 
probing
       riscv: misaligned: declare misaligned_access_speed under 
CONFIG_RISCV_MISALIGNED
       riscv: misaligned: move emulated access uniformity check in a 
function
       riscv: misaligned: add a function to check misalign trap delegability
       selftests: riscv: add misaligned access testing
       riscv: process: use unsigned int instead of unsigned long for 
put_user()
       riscv: uaccess: do not do misaligned accesses in get/put_user()

  arch/riscv/include/asm/asm-prototypes.h              |   2 +-
  arch/riscv/include/asm/cpufeature.h                  |  14 +-
  arch/riscv/include/asm/sbi.h                         |  60 +++++
  arch/riscv/include/asm/uaccess.h                     |  48 ++--
  arch/riscv/kernel/process.c                          |   2 +-
  arch/riscv/kernel/sbi.c                              |  81 ++++++-
  arch/riscv/kernel/traps_misaligned.c                 | 112 +++++++++-
  arch/riscv/kernel/unaligned_access_speed.c           |   8 +-
  arch/riscv/lib/riscv_v_helpers.c                     |  11 +-
  arch/riscv/lib/uaccess.S                             |  50 +++--
  arch/riscv/lib/uaccess_vector.S                      |  15 +-
  tools/testing/selftests/riscv/Makefile               |   2 +-
  tools/testing/selftests/riscv/misaligned/.gitignore  |   1 +
  tools/testing/selftests/riscv/misaligned/Makefile    |  12 +
  tools/testing/selftests/riscv/misaligned/common.S    |  33 +++
  tools/testing/selftests/riscv/misaligned/fpu.S       | 180 +++++++++++++++
  tools/testing/selftests/riscv/misaligned/gp.S        | 102 +++++++++
  .../testing/selftests/riscv/misaligned/misaligned.c  | 253 
++++++++++++++++++++++
  18 files changed, 917 insertions(+), 69 deletions(-)
  create mode 100644 tools/testing/selftests/riscv/misaligned/.gitignore
  create mode 100644 tools/testing/selftests/riscv/misaligned/Makefile
  create mode 100644 tools/testing/selftests/riscv/misaligned/common.S
  create mode 100644 tools/testing/selftests/riscv/misaligned/fpu.S
  create mode 100644 tools/testing/selftests/riscv/misaligned/gp.S
  create mode 100644 tools/testing/selftests/riscv/misaligned/misaligned.c