[PATCH v2 3/3] riscv: Optimize gcd() performance on RISC-V without Zbb extension

[Andrew Morton]

On Sat, 24 May 2025 23:55:19 +0800 Kuan-Wei Chiu <visitorckw at gmail.com> wrote:

> The binary GCD implementation uses FFS (find first set), which benefits
> from hardware support for the ctz instruction, provided by the Zbb
> extension on RISC-V. Without Zbb, this results in slower
> software-emulated behavior.
> 
> Previously, RISC-V always used the binary GCD, regardless of actual
> hardware support. This patch improves runtime efficiency by disabling
> the efficient_ffs_key static branch when Zbb is either not enabled in
> the kernel (config) or not supported on the executing CPU. This selects
> the odd-even GCD implementation, which is faster in the absence of
> efficient FFS.
> 
> This change ensures the most suitable GCD algorithm is chosen
> dynamically based on actual hardware capabilities.
> 
> ...
>
> --- a/arch/riscv/kernel/setup.c
> +++ b/arch/riscv/kernel/setup.c
> @@ -21,6 +21,7 @@
>  #include <linux/efi.h>
>  #include <linux/crash_dump.h>
>  #include <linux/panic_notifier.h>
> +#include <linux/jump_label.h>
>  
>  #include <asm/acpi.h>
>  #include <asm/alternative.h>
> @@ -51,6 +52,8 @@ atomic_t hart_lottery __section(".sdata")
>  ;
>  unsigned long boot_cpu_hartid;
>  
> +DECLARE_STATIC_KEY_TRUE(efficient_ffs_key);

Please let's get this into a header file, visible to the definition
site and to all users.