[PATCH v3] riscv: Fix the PAUSE Opcode for MIPS P8700.

[Charlie Jenkins]

On Wed, Jan 29, 2025 at 02:17:03PM +0100, Aleksandar Rikalo wrote:
> From: Djordje Todorovic <djordje.todorovic at htecgroup.com>
> 
> The riscv MIPS P8700 uses a different opcode for PAUSE.
> It is a ‘hint’ encoding of the SLLI instruction, with rd=0, rs1=0 and
> imm=5. It will behave as a NOP instruction if no additional behavior
> beyond that of SLLI is implemented.
> 
> Add ERRATA_MIPS and ERRATA_MIPS_P8700_PAUSE_OPCODE configs.
> Handle errata for MIPS CPUs.
> 
> Signed-off-by: Djordje Todorovic <djordje.todorovic at htecgroup.com>
> Signed-off-by: Aleksandar Rikalo <arikalo at gmail.com>
> Signed-off-by: Raj Vishwanathan4 <rvishwanathan at mips.com>

Please copy people who commented on previous versions of patches in the
new versions!

- Charlie