[PATCH v3 10/21] dt-bindings: riscv: add Smcntrpmf ISA extension description

[Conor Dooley]

On Mon, Jan 27, 2025 at 08:59:51PM -0800, Atish Patra wrote:
> Add the description for Smcntrpmf ISA extension
> 
> Signed-off-by: Atish Patra <atishp at rivosinc.com>
> ---
>  Documentation/devicetree/bindings/riscv/extensions.yaml | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index 1706a77729db..0afe47259c55 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -136,6 +136,14 @@ properties:
>              20240213 version of the privileged ISA specification. This extension
>              depends on Sscsrind, Zihpm, Zicntr extensions.
>  
> +        - const: smcntrpmf
> +          description: |
> +            The standard Smcntrpmf supervisor-level extension for the machine mode
> +            to enable privilege mode filtering for cycle and instret counters as
> +            ratified in the 20240326 version of the privileged ISA specification.
> +            The Ssccfg extension depends on this as *cfg CSRs are available only
> +            if smcntrpmf is present.

Same here, this Ssccfg dep on Smcntrpmf should be in schema.

> +
>          - const: smmpm
>            description: |
>              The standard Smmpm extension for M-mode pointer masking as
> 
> -- 
> 2.34.1
> 
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