[PATCH v3 08/21] dt-bindings: riscv: add Counter delegation ISA extensions description
Atish Patra
atishp at rivosinc.com
Mon Jan 27 20:59:49 PST 2025
Add description for the Smcdeleg/Ssccfg extension.
Signed-off-by: Atish Patra <atishp at rivosinc.com>
---
Documentation/devicetree/bindings/riscv/extensions.yaml | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index f47d829545db..1706a77729db 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -128,6 +128,14 @@ properties:
changes to interrupts as frozen at commit ccbddab ("Merge pull
request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
+ - const: smcdeleg
+ description: |
+ The standard Smcdeleg supervisor-level extension for the machine mode
+ to delegate the hpmcounters to supvervisor mode so that they are
+ directlyi accessible in the supervisor mode as ratified in the
+ 20240213 version of the privileged ISA specification. This extension
+ depends on Sscsrind, Zihpm, Zicntr extensions.
+
- const: smmpm
description: |
The standard Smmpm extension for M-mode pointer masking as
@@ -169,6 +177,14 @@ properties:
behavioural changes to interrupts as frozen at commit ccbddab
("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
+ - const: ssccfg
+ description: |
+ The standard Ssccfg supervisor-level extension for configuring
+ the delegated hpmcounters to be accessible directly in supervisor
+ mode as ratified in the 20240213 version of the privileged ISA
+ specification. This extension depends on Sscsrind, Smcdeleg, Zihpm,
+ Zicntr extensions.
+
- const: sscofpmf
description: |
The standard Sscofpmf supervisor-level extension for count overflow
--
2.34.1
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