[PATCH 3/5] irqchip/riscv-imsic: Use wmb() to order normal writes and IPI writes

[Anup Patel]

On Mon, Jan 13, 2025 at 8:39 PM Xu Lu <luxu.kernel at bytedance.com> wrote:
>
> During an IPI procedure, we need to ensure all previous write operations
> are visible to other CPUs before sending a real IPI. We use wmb() barrier
> to ensure this as IMSIC issues IPI via mmio writes.
>
> Signed-off-by: Xu Lu <luxu.kernel at bytedance.com>
> ---
>  drivers/irqchip/irq-riscv-imsic-early.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/irqchip/irq-riscv-imsic-early.c b/drivers/irqchip/irq-riscv-imsic-early.c
> index 63097f2bbadf..c6317cb557fb 100644
> --- a/drivers/irqchip/irq-riscv-imsic-early.c
> +++ b/drivers/irqchip/irq-riscv-imsic-early.c
> @@ -29,6 +29,12 @@ static void imsic_ipi_send(unsigned int cpu)
>  {
>         struct imsic_local_config *local = per_cpu_ptr(imsic->global.local, cpu);
>
> +       /*
> +        * Ensure that stores to normal memory are visible to the other CPUs
> +        * before issuing IPI.
> +        */
> +       wmb();
> +

The imsic_ipi_send() is called through ipi_mux_send_mask()
which does smp_mb__after_atomic() before calling so no need
for any barrier here. Also, barriers need to be in-pair so adding
a single barrier at random location is inappropriate.
(Refer, https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/kernel/irq/ipi-mux.c?h=v6.13-rc7#n78)

Based on the above, this patch is not needed.

Regards,
Anup