[PATCH 5/5] irqchip/aclint-sswi: Use wmb() to order normal writes and IPI writes

[Xu Lu]

During an IPI procedure, we need to ensure all previous write operations
are visible to other CPUs before sending a real IPI. We use wmb() barrier
to ensure this as ACLINT SSWI issues IPI via mmio writes.

Signed-off-by: Xu Lu <luxu.kernel at bytedance.com>
---
 drivers/irqchip/irq-thead-c900-aclint-sswi.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/irqchip/irq-thead-c900-aclint-sswi.c b/drivers/irqchip/irq-thead-c900-aclint-sswi.c
index b0e366ade427..7246a008a0f0 100644
--- a/drivers/irqchip/irq-thead-c900-aclint-sswi.c
+++ b/drivers/irqchip/irq-thead-c900-aclint-sswi.c
@@ -31,6 +31,12 @@ static DEFINE_PER_CPU(void __iomem *, sswi_cpu_regs);
 
 static void thead_aclint_sswi_ipi_send(unsigned int cpu)
 {
+	/*
+	 * Ensure that stores to normal memory are visible to the other CPUs
+	 * before issuing IPI.
+	 */
+	wmb();
+
 	writel_relaxed(0x1, per_cpu(sswi_cpu_regs, cpu));
 }
 
-- 
2.20.1