[PATCH 4/5] irqchip/timer-clint: Use wmb() to order normal writes and IPI writes

[Xu Lu]

During an IPI procedure, we need to ensure all previous write operations
are visible to other CPUs before sending a real IPI. We use wmb() barrier
to ensure this as CLINT issues IPI via mmio writes.

Signed-off-by: Xu Lu <luxu.kernel at bytedance.com>
---
 drivers/clocksource/timer-clint.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c
index 0bdd9d7ec545..8d73b45f9966 100644
--- a/drivers/clocksource/timer-clint.c
+++ b/drivers/clocksource/timer-clint.c
@@ -48,6 +48,12 @@ EXPORT_SYMBOL(clint_time_val);
 #ifdef CONFIG_SMP
 static void clint_send_ipi(unsigned int cpu)
 {
+	/*
+	 * Ensure that stores to normal memory are visible to the other CPUs
+	 * before issuing IPI.
+	 */
+	wmb();
+
 	writel(1, clint_ipi_base + cpuid_to_hartid_map(cpu));
 }
 
-- 
2.20.1