[PATCH 0/5] riscv: irqchip: Optimization of interrupt handling

[Xu Lu]

This patch series provides some optimization for the existing interrupt
handling procedure. First, it tries to make a balance between interrupt
priority and fairness to avoid interrupts with lower priority get
starved. Also, it inserts barriers to ensure the order between normal
memory writes and IPI issuing.

Xu Lu (5):
  irqchip/riscv-intc: Balance priority and fairness during irq handling
  irqchip/riscv-imsic: Add a threshold to ext irq handling times
  irqchip/riscv-imsic: Use wmb() to order normal writes and IPI writes
  irqchip/timer-clint: Use wmb() to order normal writes and IPI writes
  irqchip/aclint-sswi: Use wmb() to order normal writes and IPI writes

 drivers/clocksource/timer-clint.c            |  6 ++++
 drivers/irqchip/irq-riscv-imsic-early.c      | 37 +++++++++++++-------
 drivers/irqchip/irq-riscv-intc.c             | 32 +++++++++++++----
 drivers/irqchip/irq-thead-c900-aclint-sswi.c |  6 ++++
 4 files changed, 62 insertions(+), 19 deletions(-)

-- 
2.20.1