[PATCH v2] RISC-V: KVM: Fix csr_write -> csr_set for HVIEN PMU overflow bit

[patchwork-bot+linux-riscv at kernel.org]

Hello:

This patch was applied to riscv/linux.git (fixes)
by Anup Patel <anup at brainfault.org>:

On Wed, 27 Nov 2024 04:18:40 +0000 you wrote:
> This doesn't cause a problem currently as HVIEN isn't used elsewhere
> yet. Found by inspection.
> 
> Signed-off-by: Michael Neuling <michaelneuling at tenstorrent.com>
> Fixes: 16b0bde9a37c ("RISC-V: KVM: Add perf sampling support for guests")
> Reviewed-by: Atish Patra <atishp at rivosinc.com>
> Reviewed-by: Anup Patel <anup at brainfault.org>
> 
> [...]

Here is the summary with links:
  - [v2] RISC-V: KVM: Fix csr_write -> csr_set for HVIEN PMU overflow bit
    https://git.kernel.org/riscv/c/ea6398a5af81

You are awesome, thank you!
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