[PATCH 0/2] riscv,aplic: support for hart indexes

[Vladimir Kondratiev]

>The APLIC domain in direct mode requires "HART Index" to be
>between 0 to N - 1 where N is the number of HARTs targeted by
>the APLIC domain because the APLIC IDC structures are placed
>consecutively in the MMIO space and located based on "HART index".
>(Refer, first paragraph of the section "4.8 Interrupt delivery directly
>by the APLIC" of the ratified RISC-V AIA v1.0 specification)

Hi Anup,

Sorry, perhaps I am reading spec the wrong way. I don't see where
spec required this:

>"HART Index" to be
>between 0 to N - 1 where N is the number of HARTs targeted by
>the APLIC domain

I have a real hardware (MIPS P8700) where APLIC is in direct mode
and hart indexes are same as hart IDs, masking out cluster number.
These hart indexes as I mentioned, "0x00, 0x01, 0x10, 0x11" etc.
For delivering IRQ, for example,  to CPU2 I need to access its IDC
by hart index 0x10. Current code uses IDC at index 2 and hardware
don't work this way because there's no registers at this address.

If spec indeed requires hart indexes to be in range as you mentioned,
such hardware is not spec compliant. Is it the case?

In addition, as spec says, hart index may be different than its hart ID
and I don't see any provisioning in current code to supply this
hart index.

What am I missing?